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Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12E128DGV1/D
MC9S12E-Family Device User Guide V01.04
Freescale Semiconductor, Inc...
Original Release Date: 4 APR 2003 Revised: 04 NOV 2003
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2003
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Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12E128DGV1/D
Revision History
Version Revision Number Date
01.00 01.01 01.02 04.APR.03 24.JUN.03 9.OCT.03
Author
Original Version.
Description of Changes
Minor typo corrections. MC9S12E32 added. Added Colpitts and Pierce connections to 2.3.8. Updated input capacitance. Updated Table A-8. Changed pin name ROMONE to ROMCTL. Added S12 LRAE to Flash section. Added EXTAL VIH and VIL min/max values and hysteresis value to Oscillator Characteristics. New wording on NVM Reliability. Updated PCB layouts. Changed PP6 to PK7 on Table 4-1. Updated DAC Supply min voltage and Operating frequency. Added Non-multiplexed Address and Chip Select external bus timing.
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01.03
31.OCT.03
01.04
04.NOV.03
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2003
2
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.4 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High & Mode Pin . . . . . . . 80 2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 80 2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 80 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.9 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.10 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.11 PE4 / ECLK-- Port E I/O Pin 4 / E-Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.12 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 / Low-Byte Strobe (LSTRB) . . . . . . . 83 2.3.13 PE2 / R/W -- Port E I/O Pin 2 / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.14 PE1 / IRQ -- Port E input Pin 1 / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . . 84 2.3.15 PE0 / XIRQ -- Port E input Pin 0 / Non Maskable Interrupt Pin . . . . . . . . . . . . . 84 2.3.16 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.17 PK6 / XCS -- Port K I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.18 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.19 2.3.20 PAD[15:0] / AN[15:0] / KWAD[15:0] -- Port AD I/O Pins [15:0] . . . . . . . . . . . . . . 85 PM7 / SCL -- Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
2.3.21 PM6 / SDA -- Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.3.22 PM5 / TXD2 -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.3.23 PM4 / RXD2 -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.3.24 PM3 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.3.25 PM1 / DAO1 -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.26 PM0 / DAO2 -- Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.27 PP[5:0] / PW0[5:0] -- Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.28 PQ[6:4] / IS[2:0] -- Port Q I/O Pins [6:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.29 PQ[3:0] / FAULT[3:0] -- Port Q I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.30 PS7 / SS -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.31 PS6 / SCK -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.32 PS5 / MOSI -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.33 PS4 / MISO -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.34 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.35 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.36 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.37 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.38 PT[7:4] / IOC1[7:4]-- Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.39 PT[3:0] / IOC0[7:4]-- Port T I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.40 PU[7:6] -- Port U I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.41 PU[5:4] / PW1[5:4] -- Port U I/O Pins [5:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.42 PU[3:0] / IOC2[7:4]/PW1[3:0] -- Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . 88 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 89 2.4.2 VDDR, VSSR -- Power Supply Pins for I/O Drivers & for Internal Voltage Regulator 89 2.4.3 VDD1, VDD2, VSS1, VSS2 -- Power Supply Pins for Internal Logic . . . . . . . . . 89 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 89 2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 89 2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 89
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Section 3 System Clock Description Section 4 Modes of Operation
4.1 4.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Section 5 Resets and Interrupts
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5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.1 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Section 6 HCS12 Core Block Description
6.1 6.2 6.3 6.4 6.5 6.6 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 97 HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 97 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . 98
Section 7 Analog to Digital Converter (ATD) Block Description Section 8 Clock Reset Generator (CRG) Block Description
8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Section 9 Digital to Analog Converter (DAC) Block Description Section 10 Flash EEPROM Block Description Section 11 IIC Block Description Section 12 Oscillator (OSC) Block Description
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
Section 13 Port Integration Module (PIM) Block Description Section 14 Pulse width Modulator with Fault protection (PMF) Block Description Section 15 Pulse Width Modulator (PWM) Block Description Section 16 Serial Communications Interface (SCI) Block Description Section 17 Serial Peripheral Interface (SPI) Block Description
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Section 18 Timer (TIM) Block Description Section 19 Voltage Regulator (VREG) Block Description
19.1 19.2 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Section 20 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Appendix B Electrical Specifications
B.1 Voltage Regulator (VREG_3V3) Operating Characteristics . . . . . . . . . . . . . . . . . . 117 B.2 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . 118 B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 B.3.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
B.3.2 B.4 B.4.1 B.4.2 B.4.3 B.5 B.5.1 B.5.2 B.6 B.6.1 B.6.2 B.7 B.7.1 B.7.2 B.7.3 B.7.4 B.7.5 B.8 B.8.1 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Flash NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ATD Operating Characteristics - 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ATD Operating Characteristics - 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ATD accuracy - 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ATD accuracy - 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DAC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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Appendix C External Bus Timing Appendix D Package Information
D.1 D.2 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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Device User Guide -- 9S12E128DGV1/D V01.04
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List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 3-1 Figure 20-1 Figure 20-2 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure B-6 Figure B-7 Figure B-8 Figure C-1 Figure D-1 Order Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC9S12E-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MC9S12E256 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 23 MC9S12E128 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 24 MC9S12E64 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 25 MC9S12E32 User configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin assignments 112 LQFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 76 Pin assignments in 80 QFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 77 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Recommended PCB Layout (112 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . 118 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 153
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Device User Guide -- 9S12E128DGV1/D V01.04
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List of Tables
Table 0-1 Table 0-2 Table 0-3 Table 0-4 Table 1-1 Table 1-2 Table 1-3 Table 2-1 Table 2-2 Table 3-1 Table 4-1 Table 4-2 Table 5-1 Table 5-2 Table 20-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table 20-2 Table B-1 Table B-2 Table B-3 Table B-4 Table B-5 Table B-6 Table B-7 Table B-8 Table B-9 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 List of MC9S12E-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 MC9S12E-Family Power and Ground Connection Summary . . . . . . . . . . . . . 90 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Recommended decoupling capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . 101 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 108 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Preliminary 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Device User Guide -- 9S12E128DGV1/D V01.04
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Table B-10 Table B-11 Table B-12 Table B-14 Table B-13 Table B-15 Table B-16 Table C-1 Table C-2
5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DAC Electrical Characteristics (Operating) . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DAC Timing/Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 149 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . . 151
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Preface
The Device User Guide provides information about the MC9S12E-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes all the individual Block Guides of the implemented modules. In a effort to reduce redundancy, all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide. Table 0-1 Document References
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Block Guide
CPU12 Reference Manual HCS12 Background Debug (BDM) HCS12 Debug (DBG) HCS12 Interrupt (INT) HCS12 Multiplexed Expanded Bus Interface (MEBI) HCS12 Module Mapping Control (MMC) Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C) Clock and Reset Generator (CRG) Digital to Analog Converter: 8-Bit, 1 Channel (DAC_8B1C) 256Kbyte Flash EEPROM (FTS256K2) 128Kbyte Flash EEPROM (FTS128K1) 32Kbyte Flash EEPROM (FTS32K) Inter IC Bus (IIC) Oscillator (OSC) Port Integration Module (PIM_9E128) Pulse Modulator with Fault Protection: 15-Bit, 6 Channels (PMF_15B6C) Pulse Width Modulator: 8-Bit, 6 Channels (PWM_8B6C) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Timer: 16-Bit, 4 Channels (TIM_16B4C) Voltage Regulator (VREG_3V3)
E256 Version
V02 V04 V01 V01 V03 V04 V04 V04 V01 V01 N/A N/A V02 V02 V01 V02 V01 V04 V03 V01 V02
E128, E64 Version
V02 V04 V01 V01 V03 V04 V02 V04 V01 N/A V01 N/A V02 V02 V01 V02 V01 V03 V03 V01 V02
E32 Version
V02 V04 V01 V01 V03 V04 V04 V04 V01 N/A N/A V02 V02 V02 V01 V02 V01 V04 V03 V01 V02
Document Order Number
S12CPUV2/D S12BDMV4/D S12DBGV1/D S12INTV1/D S12MEBIV3/D S12MMCV4/D S12ATD10B16CVx/D1 S12CRGV4/D S12DAC8B1CV1/D S12FTS256K2V1/D S12FTS128K1V1/D S12FTS32KV2/D S12IICV2/D S12OSCV2/D S12PIM9E128V1/D S12PMF15B6CV2/D S12PWM8B6CV1/D S12SCIVy/D2 S12SPIV3/D S12TIM16B4CV1/D S12VREG3V3V2/D
NOTES:
1. x in S12ATD10B16CVx/D is 2 for E64 and E128, and 4 for E32 and E256. 2. y in S12SCIVy/D is 3 for E64 and E128, and 4 for E32 and E256.
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Part Number
Figure 0-1 provides an ordering number example.
MC9S12 E128 C FU
Package Option Temperature Option Device Title
Package Options FC = 64QFN FU = 80QFP PV = 112LQFP Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C
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Controller Family
Figure 0-1 Order Part Number Coding Table 0-2 lists the part number coding based on the package and temperature. Table 0-2 Part Number Coding
Part Number
MC9S12E256CFU MC9S12E256CPV MC9S12E256MFU MC9S12E256MPV MC9S12E128CFU MC9S12E128CPV MC9S12E128MFU MC9S12E128MPV MC9S12E64CFU MC9S12E64CPV MC9S12E64MFU MC9S12E64MPV MC9S12E32CFU MC9S12E32MFU
Temp.
-40C, 85C -40C, 85C -40C, 125C -40C, 125C -40C, 85C -40C, 85C -40C, 125C -40C, 125C -40C, 85C -40C, 85C -40C, 125C -40C, 125C -40C, 85C -40C, 125C
Package
80QFP 112LQFP 80QFP 112LQFP 80QFP 112LQFP 80QFP 112LQFP 80QFP 112LQFP 80QFP 112LQFP 80QFP 80QFP
Description
MC9S12E256 MC9S12E256 MC9S12E256 MC9S12E256 MC9S12E128 MC9S12E128 MC9S12E128 MC9S12E128 MC9S12E64 MC9S12E64 MC9S12E64 MC9S12E64 MC9S12E32 MC9S12E32
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Table 0-3 summarizes the package option and size configuration. Table 0-3 Package Option Summary
Package
80QFP 80QFP 80QFP 112LQFP 64QFN 80QFP
Device
MC9S12E256 MC9S12E128 MC9S12E64 MC9S12E64 MC9S12E32 MC9S12E32
Part Number
MC9S12E256 MC9S12E256 MC9S12E128 MC9S12E128 MC9S12E64 MC9S12E64 MC9S12E32 MC9S12E32
Temp.1 Options
M, C M, C M, C M, C M, C M, C M, C M, C
Flash
256K 128K 64K 32K
RAM
16K 8K 4K 2K
I/O2
60 92 60 92 60 92 44 60
112LQFP MC9S12E256 112LQFP MC9S12E128
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NOTES: 1. C: TA = 85C, f = 25MHz. M: TA= 125C, f = 25MHz 2. I/O is the sum of ports capable to act as digital input or output.
Table 0-4 List of MC9S12E-Family members
Device Flash RAM Package MEBI
E256 E128 E64 E32 256K 128K 64K 32K 16K 8K 4K 2K 112 LQFP 80 QFP 112 LQFP 80 QFP 112 LQFP 80 QFP 80 QFP 1 0 1 0 1 0 0
TIM
12 12 12 8
SCI
3 3 3 2
SPI
1 1 1 1
IIC
1 1 1 1
A/D
16 16 16 16
D/A
2 2 2 2
PWM PMF KWU
6 6 6 0 6 6 6 6 16 16 16 16
I/O
92 60 92 60 92 60 60
* Pin out explanations: -- TIM is the number of channels. -- A/D is the number of A/D channels. -- D/A is the number of D/A channels. -- PWM is the number of channels. -- PMF is the number of channels. -- KWU is the number of key wake up interrupt pins. -- I/O is the sum of ports capable to act as digital input or output. 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, K = 8, M = 7, P = 6, Q = 7, S = 8, T = 8, U = 8, AD = 16. 18 inputs provide Interrupt capability (AD = 16, IRQ, XIRQ) 80 Pin Packages: E = 2 + 2 input only, M = 7, P = 6, Q = 7, S = 8, T = 8, U = 4, AD = 16. 18 inputs provide Interrupt capability (AD = 16, IRQ, XIRQ) -- Versions with 3 SCI modules will have SCI0, SCI1 and SCI2. -- Versions with 2 SCI modules will have SCI0 and SCI1. -- Versions with 3 TIM modules will have TIM0, TIM1 and TIM2. -- Versions with 2 TIM modules will have TIM0 and TIM1.
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Section 1 Introduction
1.1 Overview
The MC9S12E-Family is a 112/80 pin low cost general purpose MCU family. All members of the MC9S12E-Family are comprised of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM, up to 16K bytes of RAM, three asynchronous serial communications interface modules (SCI), a serial peripheral interface (SPI), an Inter-IC Bus (IIC), three 4-channel 16-bit timer modules (TIM), a 6-channel 15-bit Pulse Modulator with Fault protection module (PMF), a 6-channel 8-bit Pulse Width Modulator (PWM), a 16-channel 10-bit analog-to-digital converter (ADC), and two 1-channel 8-bit digital-to-analog converters (DAC). The MC9S12E-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available on each module, 16 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. Furthermore, an on chip bandgap based voltage regulator (VREG) generates the internal digital supply voltage of 2.5V (VDD) from a 3.135V to 5.5V external supply range.
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1.2 Features
* 16-bit HCS12 CORE - HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing - - - - - * * - - - * - Module Mapping Control (MMC) Interrupt Control (INT) Background Debug Module (BDM) Debugger (DBG12) including breakpoints and change-of-flow trace buffer Multiplexed External Bus Interface (MEBI) Up to 16 port bits available for wake up interrupt function with digital filtering 32K, 64K, 128K or 256K Byte Flash EEPROM 2K, 4K, 8K or 16K Byte RAM 8-bit resolution
Wake-Up interrupt inputs Memory options
Two 1-channel Digital-to-Analog Converters (DAC)
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*
Analog-to-Digital Converter (ADC) - - 16-channel module with 10-bit resolution External conversion trigger capability Programmable input capture or output compare channels Simple PWM mode Counter Modulo Reset External Event Counting Gated Time Accumulation Programmable period and duty cycle 8-bit 6-channel or 16-bit 3-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Three independent 15-bit counters with synchronous mode Complementary channel operation Edge and center aligned PWM signals Programmable dead time insertion Integral reload rates from 1 to 16 Four fault protection shut down input pins Three current sense input pins Three asynchronous serial communication interfaces (SCI) Synchronous serial peripheral interface (SPI) Inter-IC Bus (IIC) Windowed COP watchdog Real Time interrupt Clock Monitor
*
Three 4-channel Timers (TIM) - - - - -
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*
6 PWM channels (PWM) - - - - - -
*
6-channel Pulse width Modulator with Fault protection (PMF) - - - - - - -
*
Serial interfaces - - -
*
Clock and Reset Generator (CRG) - - -
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- - - - * * - - - - - * - - - * - - - Pierce or low current Colpitts oscillator Phase-locked loop clock frequency multiplier Self Clock mode in absence of external clock Low power 0.5 to 16Mhz crystal oscillator reference clock 50MHz equivalent to 25MHz Bus Speed Input voltage range from 3.135V to 5.5V Low power mode capability Includes low voltage reset (LVR) circuitry Includes low voltage interrupt (LVI) circuitry Up to 90 I/O lines with 5V input and drive capability (112 pin package) Up to two dedicated 5V input only lines (IRQ and XIRQ) Sixteen 3.3V/5V A/D converter inputs Single-wire background debugTM mode On-chip hardware breakpoints Enhanced debug features
Operating frequency Internal 2.5V Regulator
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112-Pin LQFP or 80-Pin QFP package
Development Support.
1.3 Modes of Operation
User modes (Expanded modes are only available in the 112 pin package version) * Normal modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only)
Special Operating Modes
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*
Low power modes - - - Stop Mode Pseudo Stop Mode Wait Mode
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1.4 Block Diagram
Figure 1-1 MC9S12E-Family Block Diagram
32K - 256K Byte Flash EEPROM 2K -16K Byte RAM
VDDR VSSR BKGD PW00 PW01 PW02 PW03 PW04 PW05 FAULT0 FAULT1 FAULT2 FAULT3 IS0 IS1 IS2 PP0 PP1 PP2 PP3 PP4 PP5 PQ0 PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7
DDRP DDRQ DDRS DDRT DDRU
Voltage Regulator
MODC/TAGHI
PMF
XFC
EXTAL XTAL RESET
CRG Reset
Clock and Generation
Periodic Interrupt COP Watchdog Clock Monitor Debugger(DBG12) Breakpoints
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PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 TEST
XIRQ IRQ R/W System LSTRB/TAGLO Integration ECLK Module MODA/IPIPE0 (SIM) MODB/IPIPE1 NOACC/XCLKS XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 XCS ECS
SCI0 SCI1 SPI
RXD0 TXD0 RXD1 TXD1 MISO MOSI SCK SS IOC04 IOC05 IOC06 IOC07 IOC14 IOC15 IOC16 IOC17
DDRE
PTE
TIM0
DDRK
PTK
TIM1
Multiplexed Address/Data Bus
DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
TIM2
IOC24 IOC25 IOC26 IOC27 AN0 AN1 AN2 AN3 ADC AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 KWAD8 KWAD9 KWAD10 KWAD11 KWAD12 KWAD13 KWAD14 KWAD15 DAO0
PTU PAD PTM
PWM
PW10 PW11 PW12 PW13 PW14 PW15
MUX
PTT
PTS
PTQ
Single-wire Background Debug Module
CPU12
PTP
Multiplexed Wide Bus
Multiplexed Narrow Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADC/DAC 3.3V/5V Voltage Reference
VRH VRL VDDA VSSA
Voltage Regulator 3.3V/5V
VDDR VSSR
I/O Driver 3.3V/5V
VDDX VSSX
PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PM0 PM1
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
DAC0 PLL 2.5V
VDDPLL VSSPLL
VDD1,2 VSS1,2
DDRM
Internal Logic 2.5V SCI2 IIC
DAC1
DAO1 RXD2 TXD2 SDA SCL
DDRAD
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Signals shown in Bold are not available on the 80 Pin Package
PM3 PM4 PM5 PM6 PM7
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1.5 Device Memory Map
Table 1-1 shows the device register map of the MC9S12E-Family after reset. The following figures (, Figure 1-3, and Figure 1-4) illustrate the full device memory map with Flash and RAM.
Table 1-1 Device Register Map Overview
Address
$000 - $017 $018 $019 $01A - $01B $01C - $01F Reserved Voltage Regulator (VREG) Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) CORE (DBG) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer 16-bit 4 channels (TIM0) Reserved Analog to Digital Converter 10-bit 16 channels (ATD) Reserved Serial Communications Interface 0 (SCI0) Serial Communications Interface 1 (SCI1) Serial Peripheral Interface (SPI) Inter IC Bus Serial Communications Interface 2 (SCI2) Digital to Analog Converter 8-bit 1-channel (DAC0) Digital to Analog Converter 8-bit 1-channel (DAC1) Reserved Flash Control Register Reserved Standard Timer 16-bit 4 channels (TIM1) Reserved Standard Timer 16-bit 4 channels (TIM2) Reserved Pulse Width Modulator 8-bit 6 channels (PWM) Pulse Width Modulator with Fault 15-bit 6 channels (PMF) Port Integration Module (PIM) Reserved
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size
24 1 1 2 4 16 4 12 48 16 48 24 8 8 8 8 8 4 4 8 16 48 48 16 48 48 32 64 64 384
Freescale Semiconductor, Inc...
$020 - $02F $030 - $033 $034 - $03F $040 - $06F $070 - $07F $080 - $0AF $0B0 - $0C7 $0C8 - $0CF $0D0 - $0D7 $0D8 - $0DF $0E0 - $0E7 $0E8 - $0EF $0F0 - $0F3 $0F4 - $0F7 $0F8 - $0FF $100- $10F $110 - $13F $140 - $16F $170 - $17F $180 - $1AF $1B0 - $1DF $1E0 - $1FF $200 - $23F $240 - $27F $280 - $3FF
22
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$4000 $4000 16K Bytes RAM
Mappable to any 16K Boundary $7FFF
Freescale Semiconductor, Inc...
$8000 $8000 EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM 16K Page Window sixteen * 16K Flash EEPROM Pages
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $3FFF: 16K RAM (only 15K RAM visible $0400 - $3FFF)
Figure 1-2 MC9S12E256 User Configurable Memory Map
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$2000 $2000 $4000 $3FFF $4000 8K Bytes RAM Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
Freescale Semiconductor, Inc...
$8000 $8000 EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM 16K Page Window eight * 16K Flash EEPROM Pages
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM (only 7K RAM visible $0400 - $1FFF)
Figure 1-3 MC9S12E128 User Configurable Memory Map
24
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$3000 $3000 $4000 $3FFF $4000 4K Bytes RAM Mappable to any 4K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
Freescale Semiconductor, Inc...
$8000 $8000 EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM 16K Page Window four * 16K Flash EEPROM Pages
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K RAM visible $0400 - $0FFF)
Figure 1-4 MC9S12E64 User Configurable Memory Map
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$3000 $3700 $4000 $3FFF $4000 2K Bytes RAM Mappable to any 2K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
Freescale Semiconductor, Inc...
$8000 $8000 EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM 16K Page Window two * 16K Flash EEPROM Pages
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $07FF: 2K RAM (only 1K RAM visible $0400 - $07FF)
Figure 1-5 MC9S12E32 User configurable Memory Map
1.6 Detailed Register Map
The detailed register map of the MC9S12E-Family is listed in address order below. For detailed information about register function please refer to the appropriate block guide.
26
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0000 - $000F
Addres s $0000 Name
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Read : Bit 7 Write : Read : Bit 7 Write : Read : Bit 7 Write : Read : Bit 7 Write : Read 0 : Write : Read 0 : Write : Read 0 : Write : Read 0 : Write : Read : Bit 7 Write : Read : Bit 7 Write : Read : NOACC E Write : Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTA
6
5
4
3
2
1
Bit 0
$0001
PORTB
6
5
4
3
2
1
Bit 0
$0002
DDRA
6
5
4
3
2
1
Bit 0
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$0003
DDRB
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
$0004
Reserved
0
0
0
0
0
0
0
$0005
Reserved
0
0
0
0
0
0
0
$0006
Reserved
0
0
0
0
0
0
0
$0007
Reserved
Bit 1 6 5 4 3 2
Bit 0
$0008
PORTE
0 6 5 4 3 Bit 2
0
$0009
DDRE
0 PIPOE NECLK LSTRE RDWE
0
0
$000A
PEAR
27
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
$0000 - $000F
$000B
MODE
$000C
PUCR
$000D
RDRIV
Freescale Semiconductor, Inc...
$000E
EBICTL
$000F
Reserved
Read : MODC Write : Read : PUPKE Write : Read : RDPK Write : Read 0 : Write : Read 0 : Write :
0 MODB MODA IVIS
0 EMK EME
0
0 PUPEE
0
0 PUPBE PUPAE
0
0 RDPE
0
0 RDPB RDPA
0
0
0
0
0
0 ESTR
0
0
0
0
0
0
0
$0010 - $0014
Addres s $0010 Name
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INITRM
$0011
INITRG
$0012
INITEE
$0013
MISC
$0014
MTST0
Read 0 0 : RAMHA RAM15 RAM14 RAM13 RAM12 RAM11 L Write : Read 0 0 0 0 : REG14 REG13 REG12 REG11 Write : Read 0 0 : EE15 EE14 EE13 EE12 EE11 EEON Write : Read 0 0 0 0 : EXSTR1 EXSTR0 ROMHM ROMON Write : Read Bit 7 6 5 4 3 2 1 Bit 0 : Write :
28
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$0015 - $0016
Addres s $0015 Name Read : Write : Read : Write :
INT map 1 of 2 (HCS12 Interrupt)
Bit 7 0 Bit 6 0 Bit 5 0 WRINT ADR3 ADR2 ADR1 ADR0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ITCR
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0017
MMC map 2 of 4 (HCS12 Module Mapping Control)
Bit 7 Read : Write : Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0
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Addres s $0017
Name
MTST1
$0018 - $0018
Addres s $0018 Name Read : Write :
Miscellaneous Peripherals (Device User Guide)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Reserved
$0019 - $0019
Addres s Name Read : $0019 VREGCTRL Write :
VREG3V3 (Voltage Regulator)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS LVIE LVIF Bit 1 Bit 0
29
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Miscellaneous Peripherals (Device User Guide)
Bit 7 Bit 6 ID14 Bit 5 ID13 Bit 4 ID12 Bit 3 ID11 Bit 2 ID10 Bit 1 ID9 Bit 0 ID8
$001A - $001B
Addres s $001A Name Read : Write : Read : Write :
ID15
PARTIDH
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
$001B
PARTIDL
Freescale Semiconductor, Inc...
$001C - $001D User Guide)
Addres s $001C Name
MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 0
Bit 2
Bit 1
Bit 0
MEMSIZ0
$001D
MEMSIZ1
Read eep_sw eep_sw reg_sw0 0 : 1 0 Write : Read rom_sw rom_sw 0 0 : 1 0 Write :
ram_sw ram_sw ram_sw 2 1 0
0
0
pag_sw pag_sw 1 0
$001E - $001E
Addres s $001E Name Read : Write :
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 6 Bit 5 0 IRQE IRQEN Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
INTCR
$001F - $001F
Addres s $001F Name
INT map 2 of 2 (HCS12 Interrupt)
Bit 7 Read : PSEL7 Write : Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
HPRIO
30
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$0020 - $002F
Addres s $0020 $0021 $0022
$0023 $0024
DBG (including BKP) map 1of 1 (HCS12 Debug)
Bit 7 read DBGEN write AF read write read Bit 15 write
read write read write read write read write read write Bit 7 TBF PAGSEL Bit 15 Bit 7 14 6 13 5 12 4
Name DBGC1
-
Bit 6
ARM BF Bit 14 Bit 6 0
Bit 5
TRGSEL CF Bit 13 Bit 5
Bit 4
BEGIN 0 Bit 12 Bit 4
Bit 3
DBGBRK
Bit 2
0 TRG
Bit 1
Bit 0
CAPMOD
DBGSC
DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL -
Bit 11 Bit 3 CNT
Bit 10 Bit 2
Bit 9 Bit 1
Bit 8 Bit 0
Freescale Semiconductor, Inc...
$0025 $0026 $0027
EXTCMP 11 3 10 2 9 1 RWCEN RWBEN Bit 8 Bit 0 RWC RWB
$0028 $0029 $002A
$002B $002C $002D $002E $002F
DBGC2
BKPCT0
DBGC3
BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
read BKABEN FULL BDM TAGAB BKCEN TAGC write read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA write read PAGSEL EXTCMP write
read write read write read write read write read write Bit 15 Bit 7 PAGSEL Bit 15 Bit 7 14 6 13 5 12 4 14 6 13 5 12 4 11 3 EXTCMP 11 3 10 2 10 2
9 1
Bit 8 Bit 0
9 1
Bit 8 Bit 0
$0030 - $0031
Addres s $0030 Name Read : Write : Read : Write :
MMC map 4 of 4 (HCS12 Module Mapping Control)
Bit 7 0 Bit 6 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PPAGE
0
0
0
0
0
0
0
0
$0031
Reserved
31
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0032 - $0033
Addres s $0032 Name Read : Write : Read : Write :
PORTK
ECS
XCS
XAB19
XAB18
XAB17
XAB16
XAB15
XAB14
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
Freescale Semiconductor, Inc...
$0034 - $003F
Addres s $0034 Name
CRG (Clock and Reset Generator)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0035
$0036
$0037
$0038
$0039
$003A
$003B
Read 0 0 : SYNR SYN5 Write : Read 0 0 0 : REFDV Write : Read TOUT7 TOUT6 TOUT5 : CTFLG TEST ONLY Write : Read 0 : CRGFLG RTIF PROF Write : Read 0 0 : CRGINT RTIE Write : Read : CLKSEL PLLSEL PSTP SYSWAI Write : Read : PLLCTL CME PLLON AUTO Write : Read 0 : RTICTL RTR6 RTR5 Write :
SYN4
SYN3
SYN2
SYN1
SYN0
0
REFDV REFDV REFDV REFDV 3 2 1 0 TOUT3 TOUT2 TOUT1 TOUT0
TOUT4
LOCK LOCKIF
TRACK SCMIF
SCM
0 LOCKIE
0 SCMIE
0
ROAWA PLLWAI I 0 ACQ
CWAI
RTIWAI
COPWA I
PRE
PCE
SCME
RTR4
RTR3
RTR2
RTR1
RTR0
32
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$0034 - $003F
Addres s Name
CRG (Clock and Reset Generator)
Bit 7 Bit 6 Bit 5 0 Bit 4 0 Bit 3 0 CR2 CR1 CR0 Bit 2 Bit 1 Bit 0
Freescale Semiconductor, Inc...
Read : $003C COPCTL WCOP RSBCK Write : Read : FORBYP COPBY $003D RTIBYP TEST ONLY Write P : Read TCTL7 TCTL6 : CTCTL $003E TEST ONLY Write : Read 0 0 : $003F ARMCOP Write Bit 7 6 :
0 PLLBYP
0
0 FCM
0
TCTL5
TCTL4
TCLT3
TCTL2
TCTL1
TCTL0
0 5
0 4
0 3
0 2
0 1
0 Bit 0
$0040 - $006F
Addres s $0040 Name
TIM0 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
TIOS
$0041
CFORC
$0042
OC7M
$0043
OC7D
$0044
TCNT (hi)
$0045
TCNT (lo)
Read : IOS7 IOS6 IOS5 IOS4 Write : Read 0 0 0 0 : Write FOC7 FOC6 FOC5 FOC4 : Read : OC7M7 OC7M6 OC7M5 OC7M4 Write : Read : OC7D7 OC7D6 OC7D5 OC7D4 Write : Read Bit 15 14 13 12 : Write : Read Bit 7 6 5 4 : Write :
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
Bit 8
3
2
1
Bit 0
33
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Freescale Semiconductor, Inc.
TIM0 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0040 - $006F
Addres s $0046 Name
TSCR1
$0047
TTOV
$0048
TCTL1
$0049
Reserved
$004A
TCTL3
$004B
Reserved
$004C
TIE
$004D
TSCR2
$004E
TFLG1
$004F
TFLG2
$0050
Reserved
Read 0 0 0 0 : TEN TSWAI TSFRZ TFFCA Write : Read 0 0 0 0 : TOV7 TOV6 TOV5 TOV4 Write : Read : OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Write : Read 0 0 0 0 0 0 0 0 : Write : Read : EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 : C7I C6I C5I C4I Write : Read 0 0 0 : TOI TCRE PR2 PR1 PR0 Write : Read 0 0 0 0 : C7F C6F C5F C4F Write : Read 0 0 0 0 0 0 0 : TOF Write : Read 0 0 0 0 0 0 0 0 : Write :
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0040 - $006F
Addres s $0051 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TIM0 (Timer 16 Bit 4 Channels)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Reserved
0
0
0
0
0
0
0
0
$0052
Reserved
0
0
0
0
0
0
0
0
$0053
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$0054
Reserved
0
0
0
0
0
0
0
0
$0055
Reserved
0
0
0
0
0
0
0
0
$0056
Reserved
0
0
0
0
0
0
0
0
$0057
Reserved
$0058
TC4 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$0059
TC4 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$005A
TC5 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$005B
TC5 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
35
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Freescale Semiconductor, Inc.
TIM0 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0040 - $006F
Addres s $005C Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TC6 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$005D
TC6 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$005E
TC7 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
Freescale Semiconductor, Inc...
$005F
TC7 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
$0060
PACTL
0
0
0
0
0
0 PAOVF PAIF
$0061
PAFLG
$0062
PACNT (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$0063
PACNT (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
$0064
Reserved
0
0
0
0
0
0
0
0
$0065
Reserved
0
0
0
0
0
0
0
0
$0066
Reserved
36
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0040 - $006F
Addres s $0067 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TIM0 (Timer 16 Bit 4 Channels)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Reserved
0
0
0
0
0
0
0
0
$0068
Reserved
0
0
0
0
0
0
0
0
$0069
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$006A
Reserved
0
0
0
0
0
0
0
0
$006B
Reserved
0
0
0
0
0
0
0
0
$006C
Reserved
0
0
0
0
0
0
0
0
$006D
Reserved
0
0
0
0
0
0
0
0
$006E
Reserved
0
0
0
0
0
0
0
0
$006F
Reserved
$0070 - $007F
$0070 $007F Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
37
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Freescale Semiconductor, Inc.
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0
$0080 - $00AF
Addres s $0080 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
0
ATDCTL0
WRAP31 WRAP21 WRAP11 WRAP01
$0081
ATDCTL1
ETRIGS EL2
0
0
0
ETRIGC ETRIGC ETRIGC ETRIGC H32 H22 H12 H02 ASCIF ETRIG ASCIE
$0082
ATDCTL2
ADPU
AFFC
AWAI
Freescale Semiconductor, Inc...
ETRIGL ETRIGP E
0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
$0083
ATDCTL3
$0084
ATDCTL4
SRES8
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
0 DJM DSGN SCAN MULT CC CB CA
$0085
ATDCTL5
0 SCF ETORF FIFOR
0
CC2
CC1
CC0
$0086
ATDSTAT0
0
0
0
0
0
0
0
0
$0087
Reserved
0
0
0
0
0
0
0
0
$0088
ATDTEST0
0
0
0
0
0
0
0 SC
$0089
ATDTEST1
CCF15
CCF14
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
$008A
ATDSTAT0
38
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$0080 - $00AF
Addres s $008B Name
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CCF2 Bit 1 CCF1 Bit 0 CCF0
ATDSTAT1
$008C
ATDDIEN0
$008D
ATDDIEN1
$008E
PORTAD0
$008F
PORTAD1
$0090
ATDDR0H
$0091
ATDDR0L
$0092
ATDDR1H
$0093
ATDDR1L
$0094
ATDDR2H
$0095
ATDDR2L
Read CCF7 CCF6 CCF5 CCF4 CCF3 : Write : Read : IEN15 IEN14 IEN13 IEN12 IEN11 Write : Read : IEN7 IEN6 IEN5 IEN4 IEN3 Write : Read PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 : Write : Read PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 : Write : Read Bit15 14 13 12 11 : Write : Read Bit7 Bit6 0 0 0 : Write : Read Bit15 14 13 12 11 : Write : Read Bit7 Bit6 0 0 0 : Write : Read Bit15 14 13 12 11 : Write : Read Bit7 Bit6 0 0 0 : Write :
IEN10
IEN9
IEN8
IEN2
IEN1
IEN0
Freescale Semiconductor, Inc...
PTAD10
PTAD9
PTAD8
PTAD2
PTAD1
PTAD0
10
9
Bit8
0
0
0
10
9
Bit8
0
0
0
10
9
Bit8
0
0
0
39
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit 0 Bit8
$0080 - $00AF
Addres s $0096 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
Bit15
ATDDR3H
Bit7
Bit6
0
0
0
0
0
0
$0097
ATDDR3L
Bit15
14
13
12
11
10
9
Bit8
$0098
ATDDR4H
Freescale Semiconductor, Inc...
Bit7
Bit6
0
0
0
0
0
0
$0099
ATDDR4L
Bit15
14
13
12
11
10
9
Bit8
$009A
ATDDR5H
Bit7
Bit6
0
0
0
0
0
0
$009B
ATDDR5L
Bit15
14
13
12
11
10
9
Bit8
$009C
ATDDR6H
Bit7
Bit6
0
0
0
0
0
0
$009D
ATDDR6L
Bit15
14
13
12
11
10
9
Bit8
$009E
ATDDR7H
Bit7
Bit6
0
0
0
0
0
0
$009F
ATDDR7L
Bit15
14
13
12
11
10
9
Bit8
$00A0
ATDDR8H
40
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0080 - $00AF
Addres s $00A1 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit7 Bit 6 Bit6 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
ATDDR8L
Bit15
14
13
12
11
10
9
Bit8
$00A2
ATDDR9H
Bit7
Bit6
0
0
0
0
0
0
$00A3
ATDDR9L
Freescale Semiconductor, Inc...
Bit15
14
13
12
11
10
9
Bit8
$00A4
ATDDR10H
Bit7
Bit6
0
0
0
0
0
0
$00A5
ATDDR10L
Bit15
14
13
12
11
10
9
Bit8
$00A6
ATDDR11H
Bit7
Bit6
0
0
0
0
0
0
$00A7
ATDDR11L
Bit15
14
13
12
11
10
9
Bit8
$00A8
ATDDR12H
Bit7
Bit6
0
0
0
0
0
0
$00A9
ATDDR12L
Bit15
14
13
12
11
10
9
Bit8
$00AA ATDDR13H
Bit7
Bit6
0
0
0
0
0
0
$00AB
ATDDR13L
41
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7 Bit15 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit 0 Bit8
$0080 - $00AF
Addres s Name
Freescale Semiconductor, Inc...
Read : $00AC ATDDR14H Write : Read : $00AD ATDDR14L Write : Read : $00AE ATDDR15H Write : Read : $00AF ATDDR15L Write :
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
NOTES: 1. WRAP0-3 bits are available in version V04 of ATD10B16C 2. ETRIGSEL and ETRIGCH0-3 bits are available in version V04 of ATD10B16C
$00B0 - $00C7
$00B0 $00C7 Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
$00C8 - $00CF
Addres s $00C8 Name
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCIBDH
$00C9
SCIBDL
$00CA
SCICR1
Read : IREN TNP1 TNP0 Write : Read : SBR7 SBR6 SBR5 Write : Read : SCISWA LOOPS RSRC I Write :
SBR12
SBR11
SBR10
SBR9
SBR8
SBR4
SBR3
SBR2
SBR1
SBR0
M
WAKE
ILT
PE
PT
42
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$00C8 - $00CF
Addres s $00CB Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCICR2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
$00CC
SCISR1
0
0
0
$00CD
SCISR2
TXPOL1 RXPOL1 BRK13
RAF TXDIR
Freescale Semiconductor, Inc...
R8 T8
0
0
0
0
0
0
$00CE
SCIDRH
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
$00CF
SCIDRL
NOTES: 1. TXPOL and RXPOL bits are available in version V04 of SCI
$00D0 - $00D7
Addres s $00D0 Name
SCI1 (Asynchronous Serial Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCIBDH
$00D1
SCIBDL
$00D2
SCICR1
$00D3
SCICR2
Read : IREN TNP1 TNP0 Write : Read : SBR7 SBR6 SBR5 Write : Read : SCISWA LOOPS RSRC I Write : Read : TIE TCIE RIE Write :
SBR12
SBR11
SBR10
SBR9
SBR8
SBR4
SBR3
SBR2
SBR1
SBR0
M
WAKE
ILT
PE
PT
ILIE
TE
RE
RWU
SBK
43
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
SCI1 (Asynchronous Serial Interface)
$00D0 - $00D7
Read : Write : Read : Write : Read : Write : Read : Write :
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
$00D4
SCISR1
0
0
0
$00D5
SCISR2
TXPOL RXPOL
1
1
RAF BRK13 TXDIR
R8 T8
0
0
0
0
0
0
$00D6
SCIDRH
Freescale Semiconductor, Inc...
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
$00D7
SCIDRL
NOTES: 1. TXPOL and RXPOL are available in version V04 of SCI
$00D8 - $00DF
Addres s $00D8 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
SPI (Serial Peripheral Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPICR1
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
$00D9
SPICR2
MODFE BIDIRO N E 0
0 SPISWAI SPC0
0 SPPR2 SPPR1 SPPR0
$00DA
SPIBR
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
$00DB
SPISR
0
0
0
0
0
0
0
0
$00DC
Reserved
44
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$00D8 - $00DF
Addres s $00DD Name Read : Write : Read : Write : Read : Write :
SPI (Serial Peripheral Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPIDR
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
$00DE
Reserved
0
0
0
0
0
0
0
0
$00DF
Reserved
Freescale Semiconductor, Inc...
$00E0 - $00E7
Addres s $00E0 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
IIC (Inter-IC Bus)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
IBAD
$00E1
IBFD
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
0 IBEN IBIE MS/SL Tx/Rx TXAK RSTA TCF IAAS IBB IBAL 0 SRW
0 IBSWAI
$00E2
IBCR
RXAK IBIF
$00E3
IBSR
$00E4
IBDR
D7
D6
D5
D4
D3
D2
D1
D0
45
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
IIC (Inter-IC Bus)
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$00E0 - $00E7
Addres s $00E5 Name Read : Write : Read : Write : Read : Write :
0
Reserved
0
0
0
0
0
0
0
0
$00E6
Reserved
0
0
0
0
0
0
0
0
$00E7
Reserved
Freescale Semiconductor, Inc...
$00E8 - $00EF
Addres s $00E8 Name
SCI2 (Asynchronous Serial Interface)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCIBDH
$00E9
SCIBDL
$00EA
SCICR1
$00EB
SCICR2
$00EC
SCISR1
Read : IREN TNP1 TNP0 Write : Read : SBR7 SBR6 SBR5 Write : Read : SCISWA LOOPS RSRC I Write : Read : TIE TCIE RIE Write : Read TDRE TC RDRF : Write :
SBR12
SBR11
SBR10
SBR9
SBR8
SBR4
SBR3
SBR2
SBR1
SBR0
M
WAKE
ILT
PE
PT
ILIE
TE
RE
RWU
SBK
IDLE
OR
NF
FE
PF
46
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$00E8 - $00EF
Read : Write : Read : Write : Read : Write :
SCI2 (Asynchronous Serial Interface)
0 0 0 RAF TXDIR
$00ED
SCISR2
TXPOL1 RXPOL1 BRK13
R8 T8
0
0
0
0
0
0
$00EE
SCIDRH
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
$00EF
SCIDRL
Freescale Semiconductor, Inc...
NOTES: 1. TXPOL and RXPOL are available in version V04 of SCI
$00F0 - $00F3
Addres s $00F0 Name Read : Write : Read : Write : Read : Write : Read : Write :
DAC0 (Digital-to-Analog Converter)
Bit 7 Bit 6
DACTE DACE
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
DACC0
DJM
DSGN
DACWAI
DACOE
0
0
0
0
0
0
0
0
$00F1
DACC1
$00F2
DACD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$00F3
DACD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
47
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
DAC1 (Digital-to-Analog Converter)
Bit 7 Bit 6
DACTE DACE
$00F4 - $00F7
Addres s $00F4 Name Read : Write : Read : Write : Read : Write : Read : Write :
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
DACC0
DJM
DSGN
DACWAI
DACOE
0
0
0
0
0
0
0
0
$00F5
DACC1
Freescale Semiconductor, Inc...
$00F6
DACD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$00F7
DACD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$00F8 - $00FF
$00F8 $00FF Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
$0100 - $010F
Addres s Name
Flash Control Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read FDIVLD : $0100 FCLKDIV PRDIV8 Write : Read KEYEN NV6 : 1 $0101 FSEC Write : Read 0 0 : Reserved for $0102 Factory Test Write :
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
NV5
NV4
NV3
NV2
SEC1
SEC0
0
0
0
0
0
0
48
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0100 - $010F
Addres s $0103 Name
Flash Control Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Bit 0 0
FCNFG
$0104
FPROT
$0105
FSTAT
$0106
FCMD
$0107
Reserved for Factory Test
$0108
Reserved for Factory Test
$0109
Reserved for Factory Test
$010A
Reserved for Factory Test
$010B
Reserved for Factory Test
$010C
Reserved
Read 0 0 0 : KEYAC CBEIE CCIE C Write : Read : FPOPE NV6 FPHDIS FPHS1 FPHS0 FPLDIS N Write : Read CCIF 0 : ACCER CBEIF PVIOL BLANK R Write : Read 0 0 0 : CMDB6 CMDB5 CMDB2 Write : Read 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 : Write :
FPLS1
FPLS0
0
0
Freescale Semiconductor, Inc...
0 CMDB0
0
0
0
0
0
0
0
0
0
0
0
0
49
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
Flash Control Register
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0100 - $010F
Addres s $010D Name Read : Write : Read : Write : Read : Write :
0
Reserved
0
0
0
0
0
0
0
0
$010E
Reserved
0
0
0
0
0
0
0
0
$010F
Reserved
Freescale Semiconductor, Inc...
$0110 - $013F
$0110 $013F Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
$0140 - $016F
Addres s $0140 Name
TIM1 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
TIOS
$0141
CFORC
$0142
OC7M
$0143
OC7D
$0144
TCNT (hi)
Read : IOS7 IOS6 IOS5 IOS4 Write : Read 0 0 0 0 : Write FOC7 FOC6 FOC5 FOC4 : Read : OC7M7 OC7M6 OC7M5 OC7M4 Write : Read : OC7D7 OC7D6 OC7D5 OC7D4 Write : Read Bit 15 14 13 12 : Write :
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
Bit 8
50
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0140 - $016F
Addres s $0145 Name
TIM1 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCNT (lo)
$0146
TSCR1
$0147
TTOV
$0148
TCTL1
$0149
Reserved
$014A
TCTL3
$014B
Reserved
$014C
TIE
$014D
TSCR2
$014E
TFLG1
$014F
TFLG2
Read Bit 7 6 5 4 3 2 1 Bit 0 : Write : Read 0 0 0 0 : TEN TSWAI TSFRZ TFFCA Write : Read 0 0 0 0 : TOV7 TOV6 TOV5 TOV4 Write : Read : OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Write : Read 0 0 0 0 0 0 0 0 : Write : Read : EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 : C7I C6I C5I C4I Write : Read 0 0 0 : TOI TCRE PR2 PR1 PR0 Write : Read 0 0 0 0 : C7F C6F C5F C4F Write : Read 0 0 0 0 0 0 0 : TOF Write :
Freescale Semiconductor, Inc...
51
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
TIM1 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0140 - $016F
Addres s $0150 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
0
Reserved
0
0
0
0
0
0
0
0
$0151
Reserved
0
0
0
0
0
0
0
0
$0152
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$0153
Reserved
0
0
0
0
0
0
0
0
$0154
Reserved
0
0
0
0
0
0
0
0
$0155
Reserved
0
0
0
0
0
0
0
0
$0156
Reserved
0
0
0
0
0
0
0
0
$0157
Reserved
$0158
TC4 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$0159
TC4 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$015A
TC5 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
52
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0140 - $016F
Addres s $015B Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TIM1 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC5 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$015C
TC6 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$015D
TC6 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
Freescale Semiconductor, Inc...
$015E
TC7 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$015F
TC7 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
$0160
PACTL
0
0
0
0
0
0 PAOVF PAIF
$0161
PAFLG
$0162
PACNT (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$0163
PACNT (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
$0164
Reserved
0
0
0
0
0
0
0
0
$0165
Reserved
53
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
TIM1 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0140 - $016F
Addres s $0166 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
0
Reserved
0
0
0
0
0
0
0
0
$0167
Reserved
0
0
0
0
0
0
0
0
$0168
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$0169
Reserved
0
0
0
0
0
0
0
0
$016A
Reserved
0
0
0
0
0
0
0
0
$016B
Reserved
0
0
0
0
0
0
0
0
$016C
Reserved
0
0
0
0
0
0
0
0
$016D
Reserved
0
0
0
0
0
0
0
0
$016E
Reserved
0
0
0
0
0
0
0
0
$016F
Reserved
54
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0170 - $017F
$0110 $013F Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
$0180 - $01AF
Addres s Name
TIM2 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0180
TIOS
$0181
CFORC
$0182
OC7M
$0183
OC7D
$0184
TCNT (hi)
$0185
TCNT (lo)
$0186
TSCR1
$0187
TTOV
$0188
TCTL1
Read : IOS7 IOS6 IOS5 IOS4 Write : Read 0 0 0 0 : Write FOC7 FOC6 FOC5 FOC4 : Read : OC7M7 OC7M6 OC7M5 OC7M4 Write : Read : OC7D7 OC7D6 OC7D5 OC7D4 Write : Read Bit 15 14 13 12 : Write : Read Bit 7 6 5 4 : Write : Read : TEN TSWAI TSFRZ TFFCA Write : Read : TOV7 TOV6 TOV5 TOV4 Write : Read : OM7 OL7 OM6 OL6 Write :
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
Bit 8
3
2
1
Bit 0
0
0
0
0
0
0
0
0
OM5
OL5
OM4
OL4
55
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
TIM2 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0180 - $01AF
Addres s $0189 Name
Reserved
$018A
TCTL3
$018B
Reserved
$018C
TIE
$018D
TSCR2
$018E
TFLG1
$018F
TFLG2
$0190
Reserved
$0191
Reserved
$0192
Reserved
$0193
Reserved
Read 0 0 0 0 0 0 0 0 : Write : Read : EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 : C7I C6I C5I C4I Write : Read 0 0 0 : TOI TCRE PR2 PR1 PR0 Write : Read 0 0 0 0 : C7F C6F C5F C4F Write : Read 0 0 0 0 0 0 0 : TOF Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 0 0 : Write : Read 0 0 0 0 0 0 0 0 : Write :
Freescale Semiconductor, Inc...
56
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0180 - $01AF
Addres s $0194 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TIM2 (Timer 16 Bit 4 Channels)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Reserved
0
0
0
0
0
0
0
0
$0195
Reserved
0
0
0
0
0
0
0
0
$0196
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$0197
Reserved
$0198
TC4 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$0199
TC4 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$015A
TC5 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$019B
TC5 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$019C
TC6 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$019D
TC6 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
$019E
TC7 (hi)
Bit 15
14
13
12
11
10
9
Bit 8
57
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
TIM2 (Timer 16 Bit 4 Channels)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0180 - $01AF
Addres s $019F Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TC7 (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
$01A0
PACTL
0
0
0
0
0
0 PAOVF PAIF
$01A1
PAFLG
Freescale Semiconductor, Inc...
$01A2
PACNT (hi)
Bit 15
14
13
12
11
10
9
Bit 8
$01A3
PACNT (lo)
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
$01A4
Reserved
0
0
0
0
0
0
0
0
$01A5
Reserved
0
0
0
0
0
0
0
0
$01A6
Reserved
0
0
0
0
0
0
0
0
$01A7
Reserved
0
0
0
0
0
0
0
0
$01A8
Reserved
0
0
0
0
0
0
0
0
$01A9
Reserved
58
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0180 - $01AF
Addres s $01AA Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
TIM2 (Timer 16 Bit 4 Channels)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Reserved
0
0
0
0
0
0
0
0
$01AB
Reserved
0
0
0
0
0
0
0
0
$01AC
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$01AD
Reserved
0
0
0
0
0
0
0
0
$01AE
Reserved
0
0
0
0
0
0
0
0
$01AF
Reserved
$01B0 - $01DF
$01B0 $01DF Read : Write :
Reserved
0 0 0 0 0 0 0 0
Reserved
59
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PWM (Pulse Width Modulator)
Bit 7 0 Bit 6 0 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$01E0 - $01FF
Addres s Name
Read : $01E0 PWME Write : Read : $01E1 PWMPOL Write : Read : $01E2 PWMCLK Write : Read : $01E3 PWMPRCLK Write : Read : $01E4 PWMCAE Write : Read : $01E5 PWMCTL Write : Read : PWMTST $01E6 Test Only Write : Read : $01E7 PWMPRSC Write : Read : $01E8 PWMSCLA Write : Read : $01E9 PWMSCLB Write : Read : $01EA PWMSCNTA Write :
0
0 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
0
0 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
Freescale Semiconductor, Inc...
0 PCKB2 PCKB1 PCKB0
0 PCKA2 PCKA1 PCKA0
0
0 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
0 CON45 CON23 CON01 PSWAI PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
60
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$01E0 - $01FF
Addres s Name
PWM (Pulse Width Modulator)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Read : $01EB PWMSCNTB Write : Read : $01EC PWMCNT0 Write : Read : $01ED PWMCNT1 Write : Read : $01EE PWMCNT2 Write : Read : $01EF PWMCNT3 Write : Read : $01F0 PWMCNT4 Write : Read : $01F1 PWMCNT5 Write : Read : $01F2 PWMPER0 Write : Read : $01F3 PWMPER1 Write : Read : $01F4 PWMPER2 Write : Read : $01F5 PWMPER3 Write :
Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0
6 0 6 0 6 0 6 0 6 0 6 0
5 0 5 0 5 0 5 0 5 0 5 0
4 0 4 0 4 0 4 0 4 0 4 0
3 0 3 0 3 0 3 0 3 0 3 0
2 0 2 0 2 0 2 0 2 0 2 0
1 0 1 0 1 0 1 0 1 0 1 0
Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
61
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PWM (Pulse Width Modulator)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$01E0 - $01FF
Addres s $01F6 Name
PWMPER4
$01F7
PWMPER5
$01F8
PWMDTY0
$01F9
PWMDTY1
$01FA
PWMDTY2
$01FB
PWMDTY3
$01FC
PWMDTY4
$01FD
PWMDTY5
$01FE
PWMSDN
$01FF
Reserved
Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : Bit 7 6 Write : Read : PWMIF PWMIE Write : Read 0 0 : Write :
5
4
3
2
1
Bit 0
5
4
3
2
1
Bit 0
5
4
3
2
1
Bit 0
Freescale Semiconductor, Inc...
5
4
3
2
1
Bit 0
5
4
3
2
1
Bit 0
5
4
3
2
1
Bit 0
5
4
3
2
1
Bit 0
5
4
3
2 PWM5I N
1
Bit 0
0
PWMRSTR T
0 PWMLV L 0 0
PWM5I NL 0
PWM5E NA
0
0
0
62
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0200 - $023F
Addres s $0200 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PMF (Pulse width Modulator with Fault protection)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PMFCFG0
WP
MTG
EDGEC
EDGEB
EDGEA
INDEPC
INDEPB
INDEPA
0
ENHA
BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA
$0201
PMFCFG1
0
0
MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
$0202
PMFCFG2
Freescale Semiconductor, Inc...
0
PMFWAI PMFFRZ VLMODE SWAPC SWAPB SWAPA
$0203
PMFCFG3
$0204
PMFFCTL
FMODE3
FIE3
FMODE2
FIE2
FMODE1
FIE1
FMODE0
FIE0
0
FPINE3
0
FPINE2
0
FPINE1
0
FPINE0
$0205
PMFFPIN
0
FFLAG3
0
FFLAG2
0
FFLAG1
0
FFLAG0
$0206
PMFFSTA
$0207
PMFQSMP
QSMP3
QSMP2
QSMP1
QSMP0
$0208
PMFDMPA
DMP13
DMP12
DMP11
DMP10
DMP03
DMP02
DMP01
DMP00
$0209
PMFDMPB
DMP33
DMP32
DMP31
DMP30
DMP23
DMP22
DMP21
DMP20
$020A
PMFDMPC
DMP53
DMP52
DMP51
DMP50
DMP43
DMP42
DMP41
DMP40
63
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PMF (Pulse width Modulator with Fault protection)
Bit 7 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0200 - $023F
Addres s $020B Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
0
Reserved
0
0
$020C
PMFOUTC
OUTCTL OUTCTL OUTCTL OUTCTL OUTCTL OUTCTL 5 4 3 2 1 0
0
0
OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
$020D
PMFOUTB
Freescale Semiconductor, Inc...
0
0
DT5
DT4
DT3
DT2
DT1
DT0
$020E
PMFDTMS
0
0
ISENS
0
IPOLC IPOLB IPOLA
$020F
PMFCCTL
$0210
PMFVAL0
Bit 15
14
13
12
11
10
9
Bit 8
$0211
PMFVAL0
Bit 7
6
5
4
3
2
1
Bit 0
$0212
PMFVAL1
Bit 15
14
13
12
11
10
9
Bit 8
$0213
PMFVAL1
Bit 7
6
5
4
3
2
1
Bit 0
$0214
PMFVAL2
Bit 15
14
13
12
11
10
9
Bit 8
$0215
PMFVAL2
Bit 7
6
5
4
3
2
1
Bit 0
64
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0200 - $023F
Addres s $0216 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PMF (Pulse width Modulator with Fault protection)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PMFVAL3
Bit 15
14
13
12
11
10
9
Bit 8
$0217
PMFVAL3
Bit 7
6
5
4
3
2
1
Bit 0
$0218
PMFVAL4
Bit 15
14
13
12
11
10
9
Bit 8
Freescale Semiconductor, Inc...
$0219
PMFVAL4
Bit 7
6
5
4
3
2
1
Bit 0
$021A
PMFVAL5
Bit 15
14
13
12
11
10
9
Bit 8
$021B
PMFVAL5
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
$021C
Reserved
0
0
0
0
0
0
0
0
$021D
Reserved
0
0
0
0
0
0
0
0
$021E
Reserved
0
0
0
0
0
0
0
0
$021F
Reserved
0
PWMENA
0
0
0
0
LDOKA
PWMRIEA
$0220
PMFENCA
65
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PMF (Pulse width Modulator with Fault protection)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0200 - $023F
Addres s $0221 Name Read : PMFFQCA Write : Read : PMFCNTA Write : Read : PMFCNTA Write : Read : PMFMODA Write : Read : PMFMODA Write : Read : PMFDTMA Write : Read : PMFDTMA Write : Read : PMFENCB Write : Read : PMFFQCB Write : Read : PMFCNTB Write : Read : PMFCNTB Write :
LDFQA
HALFA
PRSCA
PWMRFA
0
Bit 14 13 12 11 10 9 Bit 8
$0222
$0223
Bit 7
6
5
4
3
2
1
Bit 0
Freescale Semiconductor, Inc...
0
Bit 14 13 12 11 10 9 Bit 8
$0224
$0225
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
Bit 11 10 9 Bit 8
$0226
$0227
Bit 7
6
5
4
3
2
1
Bit 0
$0228
PWMENB
0
0
0
0
0
LDOKB
PWMRIEB
$0229
LDFQB
HALFB
PRSCB
PWMRFB
0
Bit 14 13 12 11 10 9 Bit 8
$022A
$022B
Bit 7
6
5
4
3
2
1
Bit 0
66
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0200 - $023F
Addres s $022C Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PMF (Pulse width Modulator with Fault protection)
Bit 7 0
Bit 14 13 12 11 10 9 Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMFMODB
$022D
PMFMODB
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
Bit 11 10 9 Bit 8
$022E
PMFDTMB
Freescale Semiconductor, Inc...
$022F
PMFDTMB
Bit 7
6
5
4
3
2
1
Bit 0
$0230
PMFENCC
PWMENC
0
0
0
0
0
LDOKC
PWMRIEC
$0231
PMFFQCC
LDFQC
HALFC
PRSCC
PWMRFC
0
Bit 14 13 12 11 10 9 Bit 8
$0232
PMFCNTC
$0233
PMFCNTC
Bit 7
6
5
4
3
2
1
Bit 0
0
Bit 14 13 12 11 10 9 Bit 8
$0234
PMFMODC
$0235
PMFMODC
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
Bit 11 10 9 Bit 8
$0236
PMFDTMC
67
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PMF (Pulse width Modulator with Fault protection)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0200 - $023F
Addres s $0237 Name Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PMFDTMC
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
$0238
Reserved
0
0
0
0
0
0
0
0
$0239
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$023A
Reserved
0
0
0
0
0
0
0
0
$023B
Reserved
0
0
0
0
0
0
0
0
$023C
Reserved
0
0
0
0
0
0
0
0
$023D
Reserved
0
0
0
0
0
0
0
0
$023E
Reserved
0
0
0
0
0
0
0
0
$023F
Reserved
68
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0240 - $027F
Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PIM (Port Interface Module)
$0240
PTT
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
$0241
PTIT
$0242
DDRT
DDRT7
DDRT7
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
Freescale Semiconductor, Inc...
$0243
RDRT
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
$0244
PERT
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
$0245
PPST
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
$0246
Reserved
0
0
0
0
0
0
0
0
$0247
Reserved
$0248
PTS
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
$0249
PTIS
$024A
DDRS
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
$024B
RDRS
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
69
For More Information On This Product, Go to: www.freescale.com
Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PIM (Port Interface Module)
$0240 - $027F
Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
$024C
PERS
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
$024D
PPSS
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
$024E
WOMS
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$024F
Reserved
0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM1 PTM0
$0250
PTM
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
0
PTIM1
PTIM0
$0251
PTIM
0 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM1 DDRM0
$0252
DDRM
0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM1 RDRM0
$0253
RDRM
0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM1 PERM0
$0254
PERM
0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM1 PPSM0
$0255
PPSM
0 WOMM7 WOMM6 WOMM5 WOMM4
0
0
0
$0256
WOMM
0
0
0
0
0
0
0
0
$0257
Reserved
70
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0240 - $027F
Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
PIM (Port Interface Module)
0 0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
$0258
PTP
0
0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
$0259
PTIP
0
0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
$025A
DDRP
Freescale Semiconductor, Inc...
0
0 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
$025B
RDRP
0
0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
$025C
PERP
0
0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
$025D
PPSP
0
0
0
0
0
0
0
0
$025E
Reserved
0
0
0
0
0
0
0
0
$025F
Reserved
0 PTQ6 PTQ5 PTQ4 PTQ3 PTQ2 PTQ1 PTQ0
$0260
PTQ
0
PTIQ6
PTIQ5
PTIQ4
PTIQ3
PTIQ2
PTIQ1
PTIQ0
$0261
PTIQ
0 DDRQ6 DDRQ5 DDRQ4 DDRQ3 DDRQ2 DDRQ1 DDRQ0
$0262
DDRQ
0 RDRQ6 RDRQ5 RDRQ4 RDRQ3 RDRQ2 RDRQ1 RDRQ0
$0263
RDRQ
71
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PIM (Port Interface Module)
$0240 - $027F
Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write : Read : Write :
0 PERQ6 PERQ5 PERQ4 PERQ3 PERQ2 PERQ1 PERQ0
$0264
PERQ
0 PPSQ6 PPSQ5 PPSQ4 PPSQ3 PPSQ2 PPSQ1 PPSQ0
$0265
PPSQ
0
0
0
0
0
0
0
0
$0266
Reserved
Freescale Semiconductor, Inc...
0
0
0
0
0
0
0
0
$0267
Reserved
$0268
PTU
PTU7
PTU6
PTU5
PTU4
PTU3
PTU2
PTU1
PTU0
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
$0269
PTIU
$026A
DDRU
DDRU7
DDRU6
DDRU5
DDRU4
DDRU3
DDRU2
DDRU1
DDRU0
$026B
RDRU
RDRU7
RDRU6
RDRU5
RDRU4
RDRU3
RDRU2
RDRU1
RDRU0
$026C
PERU
PERU7
PERU6
PERU5
PERU4
PERU3
PERU2
PERU1
PERU0
$026D
PPSU
PPSU7
PPSU6
PPSU5
PPSU4
PPSU3
PPSU2
PPSU1
PPSU0
0
0
0
0 MODRR3 MODRR2 MODRR1 MODRR0
$026E
MODRR
0
0
0
0
0
0
0
0
$026F
Reserved
72
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
$0240 - $027F
Read : Write : Read : Write : Read : Write : Read : Write :
Read: Write:
PIM (Port Interface Module)
$0270
PTAD(H)
PTAD15
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
PTAD8
$0271
PTAD(L)
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PTIAD15 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD10
PTIAD9
PTIAD8
$0272
PTIAD(H)
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PTIAD7
PTIAD6
PTIAD5
PTIAD4
PTIAD3
PTIAD2
PTIAD1
PTIAD0
$0273
PTIAD(L)
$0274
DDRAD(H)
DDRAD15
DDRAD14
DDRAD13
DDRAD12
DDRAD11
DDRAD10
DDRAD9
DDRAD8
$0275
DDRAD(L)
$0276
RDRAD(H)
$0277
RDRAD(L)
$0278
PERAD(H)
$0279
PERAD(L)
Read : DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 Write : Read : RDRAD15 RDRAD14 RDRAD13 RDRAD12 RDRAD11 RDRAD10 RDRAD9 RDRAD8 Write : Read : RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 Write : Read : PERAD15 PERAD14 PERAD13 PERAD12 PERAD11 PERAD10 PERAD9 PERAD8 Write : Read : PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Write :
Read: Write:
PPSAD15 PPSAD14 PPSAD13 PPSAD12 PPSAD11 PPSAD10 PPSAD9 PPSAD8
$027A
PPSAD(H)
$027B
PPSAD(L)
$027C
PIEAD(H)
Read : PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Write : Read : PIEAD15 PIEAD14 PIEAD13 PIEAD12 PIEAD11 PIEAD10 PIEAD9 PIEAD8 Write :
73
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
PIM (Port Interface Module)
$0240 - $027F
$027D
PIEAD(L)
$027E
PIFAD(H)
$027F
PIFAD(L)
Read : PIEAD7 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 Write : Read : PIFAD15 PIFAD14 PIFAD13 PIFAD12 PIFAD11 PIFAD10 PIFAD9 Write : Read : PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 Write :
PIEAD0
PIFAD8
PIFAD0
Freescale Semiconductor, Inc...
$0280 - $03FF
Addres s $0280 - $2FF Name
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Read : Reserved Write : Read $0300 : Unimplement ed Write $03FF :
0
0
0
0
0
0
0
0
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset. The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID numbers. Table 1-2 Assigned Part ID Numbers
Device MC9S12E256 MC9S12E128 MC9S12E64 MC9S12E32 Mask Set Number TBD 2L15P 2L15P TBD Part ID1 $5000 $5102 $5200 $5300
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-3 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details. Table 1-3 Memory size registers
Device MC9S12E32 MC9S12E32 MC9S12E64 MC9S12E64 MC9S12E128 MC9S12E128 MC9S12E256 Register name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value $00 $80 $03 $80 $03 $80 $07 $81
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MC9S12E256
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
Section 2 Signal Description
2.1 Device Pinout
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Figure 2-1 Pin assignments 112 LQFP for MC9S12E-Family
76
IOC15/PT5 IOC16/PT6 IOC17/PT7 PW10/IOC24/PU0 PW11/IOC25/PU1 PW14/PU4 PW15/PU5 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PU6 PU7 PW12/IOC26/PU2 PW13/IOC27PU3 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 Signals shown in Bold are not available on the 80 Pin Package
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PM3 RXD2/PM4 TXD2/PM5 SDA/PM6 SCL/PM7 FAULT0/PQ0 FAULT1/PQ1 FAULT2/PQ2 FAULT3/PQ3 ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 VDDX VSSX ADDR4/DATA4/PB4 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 IS0/PQ4 IS1/PQ5 IS2/PQ6 MODC/TAGHI/BKGD IOC04/PT0 IOC05/PT1 IOC06/PT2 IOC07/PT3 IOC14/PT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP0/PW00 PP1/PW01 PP2/PW02 PP3/PW03 PP4/PW04 PP5/PW05 PK7/ECS/ROMCTL PK6/XCS PK5/XADDR19 PK4/XADDR18 VDD1 VSS1 PK3/XADDR17 PK2/XADDR16 PK1/XADDR15 PK0/XADDR14 PM1/DA1 PM0/DA0 PAD15/AN15/KWAD15 PAD14/AN14/KWAD14 PAD13/AN13/KWAD13 PAD12/AN12/KWAD12 PAD11/AN11/KWAD11 PAD10/AN10/KWAD10 PAD09/AN09/KWAD09 PAD08/AN08/KWAD08 VSSA VRL
MC9S12E-Family
112LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
VRH VDDA PAD07/AN07/KWAD07 PAD06/AN06/KWAD06 PAD05/AN05/KWAD05 PAD04/AN04/KWAD04 PAD03/AN03/KWAD03 PAD02/AN02/KWAD02 PAD01/AN01/KWAD01 PAD00/AN00/KWAD00 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 VSS2 VDD2 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 PS7/SS PS6/SCK PS5/MOSI PS4/MISO PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0
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PM3 RXD2/PM4 TXD2/PM5 SDA/PM6 SCL/PM7 FAULT0/PQ0 FAULT1/PQ1 FAULT2/PQ2 FAULT3/PQ3 VDDX VSSX IS0/PQ4 IS1/PQ5 IS2/PQ6 MODC/TAGHI/BKGD IOC04/PT0 IOC05/PT1 IOC06/PT2 IOC07/PT3 IOC14/PT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP0/PW00 PP1/PW01 PP2/PW02 PP3/PW03 PP4/PW04 PP5/PW05 VDD1 VSS1 PM1/DA1 PM0/DA0 PAD15/AN15/KWAD15 PAD14/AN14/KWAD14 PAD13/AN13/KWAD13 PAD12/AN12/KWAD12 PAD11/AN11/KWAD11 PAD10/AN10/KWAD10 PAD09/AN09/KWAD09 PAD08/AN08/KWAD08 VSSA VRL
MC9S12E-Family
80 QFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VRH VDDA PAD07/AN07/KWAD07 PAD06/AN06/KWAD06 PAD05/AN05/KWAD05 PAD04/AN04/KWAD04 PAD03/AN03/KWAD03 PAD02/AN02/KWAD02 PAD01/AN01/KWAD01 PAD00/AN00/KWAD00 VSS2 VDD2 PS7/SS PS6/SCK PS5/MOSI PS4/MISO PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0
Figure 2-2 Pin assignments in 80 QFP for MC9S12E-Family
IOC15/PT5 IOC16/PT6 IOC17/PT7 PW10/IOC24/PU0 PW11/IOC25/PU1 XCLKS/NOACC/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PW12/IOC26/PU2 PW13/IOC27/PU3 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
2.2 Signal Properties Summary
Table 2-1 Signal Properties
Pin Name Function 1
EXTAL XTAL XFC RESET BKGD TEST PAD[15:0]
Pin Name Function 2
-- -- -- -- MODC VPP AN[15:0] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ ECS XCS XADDR[19:14] SCL SDA TXD2 RXD2 -- DAO1 DAO0 PW0[5:0]
Pin Name Power Function 3 Domain
-- -- -- -- TAGHI -- KWAD[15:0} -- -- XCLKS MODB MODA -- TAGLO -- -- -- ROMCTL -- -- -- -- -- -- -- -- -- -- VDDPLL VDDPLL VDDPLL VDDX VDDX NA VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Internal Pull Resistor CTRL
NA NA NA None Up NA PERAD/ PPSAD PUCR PUCR Input
Description
Oscillator pins PLL loop filter pin External reset pin Background debug, mode pin, tag signal high Test pin only Port AD I/O Pins, ATD inputs, keypad Wake-up Port A I/O pin, multiplexed address/data Port B I/O pin, multiplexed address/data Port E I/O pin, access, clock select Port E I/O pin, pipe status, mode selection Port E I/O pin, pipe status, mode selection Port E I/O pin, bus clock output
Reset State
NA NA NA None Up NA Disabled Disabled Disabled Input
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PA[7:0] PB[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PK[7] PK[6] PK[5:0] PM7 PM6 PM5 PM4 PM3 PM1 PM0 PP[5:0]
While RESET is low: Down While RESET is low: Down PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERP/ PPSP Mode Dep1
Mode Dep(1) Port E I/O pin, low strobe, tag signal low Mode Dep(1) Port E I/O pin, R/W in expanded modes Up Up Up Up Up Up Up Up Up Disabled Disabled Disabled Disabled Port E input, external interrupt pin Port E input, non-maskable interrupt pin Port K I/O Pin, Emulation Chip Select Port K I/O Pin, External Chip Select Port K I/O Pins, Extended Addresses Port M I/O Pin, IIC SCL signal Port M I/O Pin, IIC SDA signal Port M I/O Pin, SCI2 transmit signal Port M I/O Pin, SCI2 receive signal Port M I/O Pin, IIC SDA signal Port M I/O Pin, DAC1 output Port M I/O Pin, DAC0 output Port P I/O Pins, PWM output
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Pin Name Function 1
PQ[6:4] PQ[3:0] PS7 PS6 PS5 PS4
Pin Name Function 2
IS[6:4] FAULT[3:0] SS SCK MOSI MISO TXD1 RXD1 TXD0 RXD0 IOC1[7:4] IOC0[7:4] -- PW1[5:4] IOC2[7:4]
Pin Name Power Function 3 Domain
-- -- -- -- -- -- -- -- -- -- -- -- -- -- PW1[3:0] VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Internal Pull Resistor CTRL
PERQ/ PPSQ PERQ/ PPSQ PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST PERT/ PPST PERU/ PPSU PERU/ PPSU PERU/ PPSU
Description
Port Q I/O Pins, IS[6:4] input Port Q I/O Pins, Fault[3:0] input Port S I/O Pin, SPI SS signal Port S I/O Pin, SPI SCK signal Port S I/O Pin, SPI MOSI signal Port S I/O Pin, SPI MISO signal Port S I/O Pin, SCI1 transmit signal Port S I/O Pin, SCI1 receive signal Port S I/O Pin, SCI0 transmit signal Port S I/O Pin, SCI0 receive signal Port T I/O Pins, timer (TIM1) Port T I/O Pins, timer (TIM0) Port U I/O Pins Port U I/O Pins, PWM outputs Port U I/O Pins, timer (TIM2), PWM outputs
Reset State
Disabled Disabled Up Up Up Up Up Up Up Up Disabled Disabled Disabled Disabled Disabled
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PS3 PS2 PS1 PS0 PT[7:4] PT[3:0] PU[7:6] PU[5:4] PU[3:0]
NOTES: 1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to the S12 MEBI Block Guide for PEAR register details.
NOTE: NOTE:
Signals shown in bold are not available in the 80 pin package. If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins: (80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
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Freescale Semiconductor, Inc.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET -- External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing The RESET pin includes an internal pull up device.
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2.3.3 TEST -- Test Pin
The TEST pin is reserved for test and must be tied to VSS in all applications.
2.3.4 XFC -- PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See appendix B.4.3.1and the CRG Block Guide for more detailed information.
2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. This pin always has an internal pull up.
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80 pin package version.
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package version.
80
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2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free cycle". This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If the input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
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Device User Guide -- 9S12E128DGV1/D V01.04
Freescale Semiconductor, Inc.
Figure 2-3 Colpitts Oscillator Connections (PE7=1)
EXTAL CDC * MCU XTAL C2 VSSPLL C1 Crystal or ceramic resonator
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* Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC
Figure 2-4 Pierce Oscillator Connections (PE7=0)
EXTAL
C1
MCU
XTAL
RB RS*
Crystal or ceramic resonator C2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer's data.
2.3.9 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
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Freescale Semiconductor, Guide -- 9S12E128DGV1/D V01.04 Inc. Device User
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. PE6 is not available in the 80 pin package version.
2.3.10 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. PE5 is not available in the 80 pin package version.
2.3.11 PE4 / ECLK-- Port E I/O Pin 4 / E-Clock Output
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PE4 is a general purpose input or output pin. In Normal Single Chip mode PE4 is configured with an active pull-up while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. In all modes except Normal Single Chip Mode, the PE4 pin is initially configured as the output connection for the internal bus clock(ECLK). ECLK is used as a timing reference and to demultiplex the address and data in expanded modes. The ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. All clocks, including the ECLK, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. The PE4 pin is initially configured as ECLK output with stretch in all expanded modes. Reference the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the ECLK is available for use in external select decode logic or as a constant speed clock for use in the external application system.
2.3.12 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)
PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. PE3 can also be configured as a Low-Byte Strobe (LSTRB). The LSTRB signal is used in write operations, so external low byte writes will not be possible until this function is enabled. LSTRB can be enabled by setting the LSTRE bit in the PEAR register. In Expanded Wide and Emulation Narrow modes, and when BDM tagging is enabled, the LSTRB function is multiplexed with the TAGLO function. When enabled a logic zero on the TAGLO pin at the falling edge of ECLK will tag the low byte of an instruction word being read into the instruction queue. PE3 is not available in the 80 pin package version.
2.3.13 PE2 / R/W -- Port E I/O Pin 2 / Read/Write
PE2 can be used as a general-purpose I/O in all modes and is configured an input with an active pull-up out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until the read/write function is enabled. The PE2 pin is not available in the 80 pin package version.
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2.3.14 PE1 / IRQ -- Port E input Pin 1 / Maskable Interrupt Pin
PE1 is always an input and can always be read. The PE1 pin is also the IRQ input used for requesting an asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ -- Port E input Pin 0 / Non Maskable Interrupt Pin
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PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a nonmaskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register (CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit. Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR network. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register.
2.3.16 PK7 / ECS / ROMCTL -- Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK bit in the MODE register is set to 1, this pin is used as the emulation chip select output (ECS). In expanded modes the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At the rising edge of RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12 MEBI Block Guide for further details. PK7 is not available in the 80 pin package version.
2.3.17 PK6 / XCS -- Port K I/O Pin 6
PK6 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK bit in the MODE register is set to 1, this pin is used as an external chip select signal for most external accesses that are not selected by ECS. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12 MEBI Block Guide for further details. PK6 is not available in the 80 pin package version.
2.3.18 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]
PK[5:0] are general purpose input or output pins. In MCU expanded modes of operation, when the EMK bit in the MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external bus. There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12 MEBI Block Guide for further details. PK[5:0] are not available in the 80 pin package version.
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2.3.19 PAD[15:0] / AN[15:0] / KWAD[15:0] -- Port AD I/O Pins [15:0]
PAD[15:0] are the analog inputs for the analog to digital converter (ADC). They can also be configured as general purpose digital input or output pin. When enabled as digital inputs or outputs, the PAD[15:0] can also be configured as Keypad Wake-up pins (KWU) and generate interrupts causing the MCU to exit STOP or WAIT mode. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the ATD_10B16C Block Guide for information about pin configurations.
2.3.20 PM7 / SCL -- Port M I/O Pin 7
PM7 is a general purpose input or output pin. When the IIC module is enabled it becomes the serial clock line (SCL) for the IIC module (IIC). While in reset and immediately out of reset the PM7 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the IIC Block Guide for information about pin configurations.
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2.3.21 PM6 / SDA -- Port M I/O Pin 6
PM6 is a general purpose input or output pin. When the IIC module is enabled it becomes the Serial Data Line (SDL) for the IIC module (IIC). While in reset and immediately out of reset the PM6 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the IIC Block Guide for information about pin configurations.
2.3.22 PM5 / TXD2 -- Port M I/O Pin 5
PM5 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) transmitter is enabled the PM5 pin is configured as the transmit pin TXD2 of SCI2. While in reset and immediately out of reset the PM5 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.23 PM4 / RXD2 -- Port M I/O Pin 4
PM4 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) receiver is enabled the PM4 pin is configured as the receive pin RXD2 of SCI2. While in reset and immediately out of reset the PM4 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.24 PM3 -- Port M I/O Pin 3
PM3 is a general purpose input or output pin. While in reset and immediately out of reset the PM3 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide for information about pin configurations.
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2.3.25 PM1 / DAO1 -- Port M I/O Pin 1
PM1 is a general purpose input or output pin. When the Digital to Analog module 1 (DAC1) is enabled the PM1 pin is configured as the analog output DA01 of DAC1. While in reset and immediately out of reset the PM1 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the DAC_8B1C Block Guide for information about pin configurations.
2.3.26 PM0 / DAO2 -- Port M I/O Pin 0
PM0 is a general purpose input or output pin. When the Digital to Analog module 2 (DAC2) is enabled the PM0 pin is configured as the analog output DA02 of DAC2. While in reset and immediately out of reset the PM0 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the DAC_8B1C Block Guide for information about pin configurations.
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2.3.27 PP[5:0] / PW0[5:0] -- Port P I/O Pins [5:0]
PP[5:0] are general purpose input or output pins. When the Pulse width Modulator with Fault protection (PMF) is enabled the PP[5:0] output pins, as a whole or as pairs, can be configured as PW0[5:0] outputs. While in reset and immediately out of reset the PP[5:0] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PMF_15B6C Block Guide for information about pin configurations.
2.3.28 PQ[6:4] / IS[2:0] -- Port Q I/O Pins [6:4]
PQ[6:4] are general purpose input or output pins. When enabled in the Pulse width Modulator with Fault protection module (PMF), the PQ[6:4] pins become the current status input pins, IS[2:0], for top/bottom pulse width correction. While in reset and immediately out of reset PP[5:0] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PMF_15B6C Block Guide for information about pin configurations.
2.3.29 PQ[3:0] / FAULT[3:0] -- Port Q I/O Pins [3:0]
PQ[3:0] are general purpose input or output pins. When enabled in the Pulse width Modulator with Fault protection module (PMF), the PQ[3:0] pins become the Fault protection inputs pins, FAULT[3:0], of the PMF. While in reset and immediately out of reset the PQ[3:0] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PMF_15B6C Block Guide for information about pin configurations.
2.3.30 PS7 / SS -- Port S I/O Pin 7
PS7 is a general purpose input or output. When the Serial Peripheral Interface (SPI) is enabled PS7 becomes the slave select pin SS. While in reset and immediately out of reset the PS7 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin configurations.
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2.3.31 PS6 / SCK -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS6 becomes the serial clock pin, SCK. While in reset and immediately out of reset the PS6 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin configurations.
2.3.32 PS5 / MOSI -- Port S I/O Pin 5
PS5 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS5 is the master output (during master mode) or slave input (during slave mode) pin. While in reset and immediately out of reset the PS5 pin is configured as a high impedance input pin Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin configurations.
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2.3.33 PS4 / MISO -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS4 is the master input (during master mode) or slave output (during slave mode) pin. While in reset and immediately out of reset the PS4 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin configurations.
2.3.34 PS3 / TXD1 -- Port S I/O Pin 3
PS3 is a general purpose input or output. When the Serial Communications Interface 1 (SCI1) transmitter is enabled the PS3 pin is configured as the transmit pin, TXD1, of SCI1. While in reset and immediately out of reset the PS3 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.35 PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output. When the Serial Communications Interface 1 (SCI1) receiver is enabled the PS2 pin is configured as the receive pin RXD1 of SCI1. While in reset and immediately out of reset the PS2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.36 PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) transmitter is enabled the PS1 pin is configured as the transmit pin, TXD0, of SCI0. While in reset and immediately out of reset the PS1 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
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2.3.37 PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) receiver is enabled the PS0 pin is configured as the receive pin RXD0 of SCI0. While in reset and immediately out of reset the PS0 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.38 PT[7:4] / IOC1[7:4]-- Port T I/O Pins [7:4]
PT[7:4] are general purpose input or output pins. When the Timer system 1 (TIM1) is enabled they can also be configured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and immediately out of reset the PT[7:4] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the TIM_16B4C Block Guide for information about pin configurations.
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2.3.39 PT[3:0] / IOC0[7:4]-- Port T I/O Pins [3:0]
PT[3:0] are general purpose input or output pins. When the Timer system 0 (TIM0) is enabled they can also be configured as the TIM0 input capture or output compare pins IOC0[7-4]. While in reset and immediately out of reset the PT[3:0] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the TIM_16B4C Block Guide for information about pin configurations.
2.3.40 PU[7:6] -- Port U I/O Pins [7:6]
PU[7:6] are general purpose input or output pins. While in reset and immediately out of reset the PU[7:6] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 for information about pin configurations. PU[7:6] are not available in the 80 pin package version.
2.3.41 PU[5:4] / PW1[5:4] -- Port U I/O Pins [5:4]
PU[5:4] are general purpose input or output pins. When the Pulse Width Modulator (PWM) is enabled the PU[5:4] output pins, individually or as a pair, can be configured as PW1[5:4] outputs. While in reset and immediately out of reset the PU[5:4] pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PWM_8B6C Block Guide for information about pin configurations. PU[5:4] are not available in the 80 pin package version.
2.3.42 PU[3:0] / IOC2[7:4]/PW1[3:0] -- Port U I/O Pins [3:0]
PU[3:0] are general purpose input or output pins. When the Timer system 2 (TIM2) is enabled they can also be configured as the TIM2 input capture or output compare pins IOC2[7-4]. When the Pulse Width Modulator (PWM) is enabled the PU[3:0] output pins, individually or as a pair, can be configured as PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM function is selected. While in reset and immediately out of reset the PU[3:0] pins are configured as a high
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impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide, TIM_16B4C Block Guide, and the PWM_8B6C Block Guide for information about pin configurations.
2.4 Power Supply Pins
2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded.
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2.4.2 VDDR, VSSR -- Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 -- Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.
2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter.
2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator.
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Table 2-2 MC9S12E-Family Power and Ground Connection Summary
Mnemonic
VDD1 VDD2 VSS1 VSS2 VDDR VSSR VDDX VSSX VDDA VSSA
Nominal Voltage
2.5 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 2.5 V 0V
Description
Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. External power and ground, supply to internal voltage regulator. To disable voltage regulator attach VDDR to VSSR. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converter, the reference for the internal voltage regulator and the digital-to-analog converters, allows the supply voltage to the A/D to be bypassed independently. Reference voltage high for the ATD converter, and DAC. Reference voltage low for the ATD converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.
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VRH VRL VDDPLL VSSPLL
NOTE:
All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for details on clock generation.
HCS12 CORE
BDM CPU MMC DBG
Core Clock
MEBI INT
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Flash RAM ATD DAC EXTAL IIC PIM OSC XTAL CRG Bus Clock Oscillator Clock PMF PWM SCI0, SCI1, SCI2 SPI TIM0, TIM1, TIM2 VREG
Figure 3-1 Clock Connections
Table 3-1Clock Selection Based on PE7
PE7 = XCLKS
1 0
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12E-Family. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device.
4.2 Chip Configuration Summary
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The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0 0 0 0 1 1 1 1
PE6 = MODB
0 0 1 1 0 0 1 1
PE5 = MODA
0 1 0 1 0 1 0 1
PK7 = ROMCTL
X 0 1 X 0 1 X 0 1 X 0 1
ROMON Bit
1 1 0 0 1 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 MEBI Block Guide. Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1 0
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
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4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * * * Protection of the contents of FLASH, Operation in single-chip mode, Operation from external memory with internal FLASH disabled.
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The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to
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an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator (CRG) Block Guide.
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
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4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. System resets can be generated through external control of the RESET pin, through the clock and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
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Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFE8 to $FFEF $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFC8 to $FFCD $FFC6, $FFC7 $FFC4, $FFC5 CRG PLL lock CRG Self Clock Mode Standard Timer 0 channel 4 Standard Timer 0 channel 5 Standard Timer 0 channel 6 Standard Timer 0 channel 7 Standard Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI SCI0 SCI1 SCI2 ATD Port AD (KWU)
Interrupt Source
External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt
CCR Mask
None None None None None X-Bit I-Bit I-Bit Reserved I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved I-Bit I-Bit
Local Enable
None COPCTL (CME, FCME) COP rate select None None None INTCR (IRQEN) CRGINT (RTIE) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL(PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) SCICR2 (TIE, TCIE, RIE, ILIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) PTADIF (PTADIE) PLLCR (LOCKIE) PLLCR (SCMIE)
HPRIO Value to Elevate
- - - - - - $F2 $F0 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $CE $C6 $C4
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$FFC2, $FFC3 $FFC0, $FFC1 $FFBA to $FFBF $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9 FLASH IIC Bus
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Reserved I-Bit Reserved I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved FCNFG (CCIE, CBEIE) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL (PAOVI) PACTL (PAI) $B8 $B6 $B4 $B2 $B0 $AE $AC $AA IBCR (IBIE) $C0
Standard Timer 1 channel 4 Standard Timer 1 channel 5 Standard Timer 1 channel 6 Standard Timer 1 channel 7 Standard Timer 1 overflow Standard Timer 1 Pulse accumulator overflow Standard Timer 1 Pulse accumulator input edge Standard Timer 2 channel 4 Standard Timer 2 channel 5 Standard Timer 2 channel 6 Standard Timer 2 channel 7 Standard Timer overflow Standard Timer 2 Pulse accumulator overflow Standard Timer 2 Pulse accumulator input edge PMF Generator A Reload PMF Generator B Reload PMF Generator C Reload PMF Fault 0 PMF Fault 1 PMF Fault 2 PMF Fault 3 VREG LVI PWM Emergency Shutdown
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$FFA6, $FFA7 $FFA4, $FFA5 $FFA2, $FFA3 $FFA0, $FFA1 $FF9E, $FF9F $FF9C, $FF9D $FF9A, $FF9B $FF98, $FF99 $FF96, $FF97 $FF94, $FF95 $FF92, $FF93 $FF90, $FF91 $FF8E, $FF8F $FF8C, $FF8D $FF8A, $FF8B $FF88, $FF89 $FF80 to $FF87
I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved
TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL (PAOVI) PACTL (PAI) PMFENCA (PWMRIEA) PMFENCB (PWMRIEB) PMFENCC (PWMRIEC) PMFFCTL (FIE0) PMFFCTL (FIE1) PMFFCTL (FIE2) PMFFCTL (FIE3) CTRL0 (LVIE) PWMSDN(PWMIE)
$A6 $A4 $A2 $A0 $9E $9C $9A $98 $96 $94 $92 $90 $8E $8C $8A $88
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. Table 5-2 Reset Summary
Reset
Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset
Priority
1 1 1 2
Source
CRG Module RESET pin VREG Module CRG Module
Vector
$FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD
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Table 5-2 Reset Summary
COP Watchdog Reset 3 CRG Module $FFFA, $FFFB
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM Block Guide for reset configurations of all peripheral module ports. Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit. When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module. When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface module.
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6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module. Note that V04 of the ATD has an external trigger (ETRIG) function which is tied off and not available for use.
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Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block Guide for voltage level specifications. 3F.
8.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7).
Section 9 Digital to Analog Converter (DAC) Block Description
There are two digital to analog converter modules (DAC0, DAC1). Consult the DAC Block Guide for information about the DAC Module.
Section 10 Flash EEPROM Block Description
Consult the FTS32K Block Guide for information about the flash module for the MC9S12E32. Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E64. Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E128.
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Consult the FTS256K2 Block Guide for information about the flash module for the MC9S12E256. The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D) . It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device.
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Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the IIC Module.
Section 12 Oscillator (OSC) Block Description
Consult the OSC Block Guide for information about the Oscillator module.
Section 13 Port Integration Module (PIM) Block Description
Consult the PIM_9E128 Block Guide for information about the Port Integration Module.
Section 14 Pulse width Modulator with Fault protection (PMF) Block Description
Consult the PMF_15B6C Block Guide for information about the Pulse width Modulator with Fault protection Module.
Section 15 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B6C Block Guide for information about the Pulse Width Modulator Module.
Section 16 Serial Communications Interface (SCI) Block
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Description
There are three Serial Communications Interface modules (SCI0, SCI1, SCI2). Consult the SCI Block Guide for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block Description
Consult the SPI Block Guide for information about the Serial Peripheral Interface module.
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Section 18 Timer (TIM) Block Description
There are three timer modules (TIM0, TIM1, TIM2). Consult the TIM_16B4C Block Guide for information about the Timer module.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG Block Guide for information about the dual output linear voltage regulator.
19.1 VREGEN
On the MC9S12E-Family the regulator enable signal (VREGEN) is not available externally and is connected internally to VDDR.
19.2 VDD1, VDD2, VSS1, VSS2
In both the 112 pin LQFP and the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. This allows systems to employ better supply routing and further decoupling.
Section 20 Printed Circuit Board Layout Proposals
The Printed Circuit Board (PCB) must be carefully laid out to ensure proper operation of the voltage regulator as well as the MCU itself. The following rules must be observed: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6).
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* * * * * * Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins. Table 20-1 Recommended decoupling capacitor choice
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Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 Q1
Purpose
VDD1 filter cap VDD2 filter cap (80 QFP only) VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap DC cutoff cap PLL loop filter res Quartz
Type
ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value
100 - 220nF 100 - 220nF 100nF >=100nF 100nF >=100nF
See PLL specification chapter
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Figure 20-1 Recommended PCB Layout (112 LQFP) NOTE: Oscillator in Colpitts mode.
VDD1
C1 VSS1 VSSA C3 VDDA
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VDDX C6 VSSX
VSS2 C2 VDD2
VSSR C4 VDDR C5 C9 R1 C10 C11 VSSPLL VDDPLL C8 Q1 C7
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Figure 20-2 Recommended PCB Layout (80 QFP) NOTE: Oscillator in Colpitts mode.
VSSA C3 VSS1
VDD1
C1
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VDDA
VDDX C6 VSSX
VSS2
C2 VDD2
VSSR
C4 C5
VDDR
C11
C8
Q1
C7
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C9
R1
C10
VSSPLL VDDPLL
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. The part is specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the part is not tested in production test in the intermediate range.
NOTE:
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This supplement contains the most accurate electrical information for the MC9S12E-Family microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE: This classification will be added at a later release of the specification
P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12E-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and D/A converter. The VDDX, VSSX pair supplies the I/O pins The VDDR, VSSR pair supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic. VDDPLL, VSSPLL supply the oscillator and the PLL.
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VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
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A.1.3 Pins
There are four groups of functional pins. A.1.3.1 3.3V/5V I/O pins Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. A.1.3.2 Analog Reference This group of pins is comprised of the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings
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Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage1 PLL Supply Voltage (1) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 2 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL3 Instantaneous Maximum Current Single pin limit for TEST4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 - 40 - 40 - 65
Max
6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 125 140 155
Unit
V V V V V V V V V mA mA mA C C C
IDL I
DT
TA TJ Tstg
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 3. These pins are internally clamped to VSSPLL and VDDPLL 4. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model Description
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Maximum input voltage limit
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5 7.5
Unit
Ohm pF
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Ohm pF
Latch-up
V V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
1 2 3 4
C
C C C C
Rating
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at 125C positive negative Latch-up Current at 27C positive negative
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
5
C
ILAT
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
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NOTE: Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage1 PLL Supply Voltage (1) Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA
Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus TJ
Min
3.135 2.35 2.35 -0.1 -0.1 0.5 0.25 -40
Typ
3.3/5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 16 25 140
Unit
V V V V V MHz MHz C
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Oscillator Bus Frequency2 Operating Junction Temperature Range
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The given operating range applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered:
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1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i
Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
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V DD5 - V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Table A-5 Thermal Package Characteristics1
Num
1 2 3 4 5 6
C
T T T T T T T T T T
Rating
Thermal Resistance LQFP112, single sided PCB2 Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 Junction to Board LQFP112 Junction to Case LQFP112 Junction to Package Top LQFP112 Thermal Resistance QFP 80, single sided PCB Thermal Resistance QFP 80, double sided PCB with 2 internal planes Junction to Board QFP80 Junction to Case QFP80 Junction to Package Top QFP80
Symbol
JA JA JB JC JT JA JA JB JC JT
Min
- - - - - - - - - -
Typ
- - - - - - - - - -
Max
54 41 31 11 2 51 41 27 14 3
Unit
oC/W
oC/W
oC/W
o o
C/W C/W
oC/W
o
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7 8 9 10
C/W
oC/W
oC/W oC/W
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-3 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
VIH VIH VIL VIL VHYS I
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
2 3
P T C
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4
P
Input Leakage Current (pins in high ohmic input mode)1 or V V =V
in DD5 SS5
in
-2.5
-
2.5
5 6 7 8 9 10 11 12 13 14 15 16
C P C P P C P C D T P P
Output High Voltage (pins in output mode) Partial Drive IOH = -2mA Output High Voltage (pins in output mode) Full Drive IOH = -10mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) Full Drive IOL = +10mA Internal Pull Up Device Current, tested at VIL Max. Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at V Min.
IH
VOH VOH VOL VOL IPUL IPUH IPDH IPDL Cin IICS IICP tPIGN tPVAL
VDD5 - 0.8 VDD5 - 0.8 -10 10
6
0.8 0.8 -130 130 2.5 25 3
V V V V A A A A pF mA s s
Internal Pull Down Device Current, tested at VIL Max. Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port AD Interrupt Input Pulse filtered3 Port AD Interrupt Input Pulse passed(3)
-2.5 -25
-
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 Preliminary 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
C
P T Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
VIH VIH VIL VIL VHYS Iin
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
2 3
P T C
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4
P
Input Leakage Current (pins in high ohmic input mode)1 or V V =V
in DD5 SS5
-2.5
-
2.5
5 6 7 8 9 10 11 12 13 14 15 16
C P C P P C P C D T P P
Output High Voltage (pins in output mode) Partial Drive IOH = -0.75mA Output High Voltage (pins in output mode) Full Drive IOH = -4.5mA Output Low Voltage (pins in output mode) Partial Drive IOL = +0.9mA Output Low Voltage (pins in output mode) Full Drive IOL = +5.5mA Internal Pull Up Device Current, tested at VIL Max. Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at VIL Max. Input Capacitance Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port AD Interrupt Input Pulse filtered3 Port AD Interrupt Input Pulse passed(3)
VOH VOH VOL VOL IPUL IPUH IPDH IPDL Cin IICS IICP tPIGN tPVAL
VDD5 - 0.4 VDD5 - 0.4 -6 6
6
0.4 0.4 -60 60 2.5 25 3
V V V V A A A A pF mA s s
-2.5 -25
-
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
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Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
C
P
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled only RTI enabled Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Pseudo Stop Current (RTI and COP disabled) (1),(2) -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Stop Current
(2)
Symbol
IDD5 IDDW
Min
Typ
Max
65 40 5
Unit
mA
2
P P C C C C C C C C P C C P C P C P C P C C P C P C P
mA
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3
IDDPS
570 600 650 750 850 1200 1500 370 400 450 550 600 650 800 850 1200 12 30 100 130 160 200 350 400 600
A
500 A
4
IDDPS
1600 2100 5000
5
-40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
100 A
IDDS
1200 1700 5000
NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed
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Appendix B Electrical Specifications
B.1 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator. Table 20-2 VREG_3V3 - Operating Conditions
Num
1 2
C
P P
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode Output Voltage PLL Full Performance Mode Reduced Power Mode2 Reduced Power Mode3 Shutdown Mode Low Voltage Interrupt5 Assert Level Deassert Level Low Voltage Reset6 Assert Level Deassert Level Power-on Reset7 Assert Level Deassert Level
Symbol
VVDDR,A IREG
Min
3.135 -- -- 2.35 1.6 --
Typical
-- 20 12 2.5 2.5
1
Max
5.5 50 40 2.75 2.75 --
Unit
V A A V V V V V V V
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3
P
VDD
4
P
VDDPLL
2.35 2.0 1.6 --
2.5 2.5 2.5
4
2.75 2.75 2.75 --
5
P
VLVIA VLVID VLVRA VLVRD VPORA VPORD
4.1 4.25
4.37 4.52
4.66 4.77 -- 2.55
V V
5
P
2.25 --
-- --
V V
7
C
0.97 --
-----
-- 2.05
V V
NOTES: 1. High Impedance Output 2. Current IDDPLL = 1mA (Colpitts Oscillator) 3. Current IDDPLL = 3mA (Pierce Oscillator) 4. High Impedance Output 5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 6. Monitors VDD, active only in Full Performance Mode. VLVRA and VPORD must overlap 7. Monitors VDD. Active in all modes.
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice.
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B.2 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1. Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) V
VLVID VLVIA VDD VDDA
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VLVRD VLVRA VPORD
t
LVI
POR
LVI enabled
LVI disabled due to LVR
LVR
B.3 Output Loads
B.3.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.
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B.3.2 Capacitive Loads
The capacitive loads are specified in Table B-1. Ceramic capacitors with X7R dielectricum are required. Table B-1 Voltage Regulator - Capacitive Loads
Num
1 2
Characteristic
VDD external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext
Min
200 90
Typical
440 220
Max
12000 5000
Unit
nF nF
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B.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
B.4.1 Startup
Table B-2 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table B-2 Startup Characteristics
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Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8
C
T T D D D D P P POR release level POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS VLVRR VLVRA
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 2.25 2.55 196
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, IRQ edge-sensitive mode Wait recovery startup time LVR release level LVR assert level
nosc ns tcyc V V
B.4.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.4.1.2 LVR The release level VLVRR and the assert level VLVRA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. B.4.1.3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.
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B.4.1.4 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. B.4.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. B.4.1.6 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
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B.4.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table B-3 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
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Num C
1a 1b 2 3 4 5 6 7 8 9 10 11 12 13
Rating
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS VIH,EXTAL VIH,EXTAL VIL,EXTAL VIL,EXTAL VHYS,EXTAL
Min
0.5 0.5 100
Typ
Max
16 40
Unit
MHz MHz A
C Crystal oscillator range (Colpitts) C Crystal oscillator range (Pierce) 1 P Startup Current C Oscillator start-up time (Colpitts) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency 4 D External square wave pulse width low(4) D External square wave pulse width high(4) D External square wave rise time(4) D External square wave fall time(4) D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin
82 0.45 50 0.5 9.5 9.5 100
1003 2.5 200 50
ms s KHz MHz ns ns
1 1 7 1.1 0.7*VDDPLL VDDPLL + 0.3 0.3*VDDPLL VSSPLL - 0.3 250
ns ns pF V V V V V mV
P EXTAL Pin Input High Voltage(4) T EXTAL Pin Input High Voltage(4)
14
P EXTAL Pin Input Low Voltage(4) T EXTAL Pin Input Low Voltage(4)
15
C EXTAL Pin Input Hysteresis(4)
NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. fosc = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce oscillator/external clock mode is selected
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B.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. B.4.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
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VDDPLL Cs fosc fref 1 refdv+1 fcmp R Phase K Detector Loop Divider 1 synr+1
XFC Pin
VCO KV fvco
1 2
Figure B-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table B-4. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V ( 60 - 50 ) ----------------------- 100
KV = K1 e
= - 100 e
= -90.48MHz/V
The phase detector relationship is given by:
K = - i ch K V
ich is the current in tracking mode.
124
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The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------- ;( = 0.9 ) 10 4 10 2 + 1 + fC < 25kHz
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
= 50
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With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz:
2 n fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K
The capacitance Cs can now be calculated as:
2 - 0.516 C s = --------------------- -------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
B.4.3.2 Jitter Information
Cp = 470pF
The basic functionality of the PLL is shown in Figure B-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-3.
NOTE:
This section is under construction
The basic functionality of the PLL is shown in Figure B-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
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accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-3.
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
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Figure B-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t min ( N ) t max ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
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J(N)
1
5
10
20
N
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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Table B-4 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
P D D D D D C D D D D D D C C
Rating
Self Clock Mode frequency VCO locking range Lock Detector transition from Acquisition to Tracking mode Lock Detection Un-Lock Detection Lock Detector transition from Tracking to Acquisition mode PLLON Total Stabilization delay (Auto Mode) 2 PLLON Acquisition mode stabilization delay (2) PLLON Tracking mode stabilization delay (2) Fitting parameter VCO loop gain Fitting parameter VCO loop frequency Charge pump current acquisition mode Charge pump current tracking mode Jitter fit parameter 1(2) Jitter fit parameter 2(2)
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 50 4 1.5 2.5 8
Unit
MHz MHz %1 %(1) %(1) %(1) ms ms ms MHz/V MHz A A
0.5 0.3 0.2 -100 60 38.5 3.5 1.1 0.13
% %
NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
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B.5 Flash NVM
B.5.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV register. The frequency of this clock must be set within the limits specified as fNVMOP.
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The minimum program and erase times shown in Table B-5 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
B.5.1.1 Single Word Programming The programming time for single word programming is dependent on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 --------f bus f NVMOP
B.5.1.2 Row Programming Flash programming where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 --------f bus f NVMOP
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Row programming is more than 2 times faster than single word programming. B.5.1.3 Sector Erase Erasing a 512 byte Flash sector takes:
The setup times can be ignored for this operation.
1 t era 4000 --------------------f NVMOP
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B.5.1.4 Mass Erase Erasing a NVM block takes:
The setup times can be ignored for this operation. B.5.1.5 Blank Check
1 t mass 20000 --------------------f NVMOP
The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
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t check location t cyc + 10 t cyc
Table B-5 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8 9
C
D D D P D D P P D
Rating
External Oscillator Clock Bus frequency for Programming or Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time for 32 Words Sector Erase Time Mass Erase Time Blank Check Time Flash per block
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass t check
Min
0.5 1 150 462 20.42 678.42 204 1004 115
Typ
Max
501
Unit
MHz MHz
200 74.53 313 1035.53 26.73 1333 327786
kHz s s s ms ms tcyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP. 5. Minimum time, if first word in the array is not blank 6. Maximum time to complete check on an erased block.
B.5.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures.
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The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE: All values shown in Table B-6 are target values and subject to further extensive characterization. Table B-6 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
C
C C C
Rating
Data Retention at an average junction temperature of TJavg = 85C Data Retention at a junction temperature of TJ = 140C Flash number of Program/Erase cycles
Symbol
tNVMRET tNVMRET nFLPE
Min
15 10 10,000
Typ
Max
Unit
Years Years Cycles
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2 3
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B.6 SPI Characteristics
This section provides electrical parametrics and ratings for the SPI. In Table B-7 the measurement conditions are listed. Table B-7 Measurement Conditions
Description
Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points
Value
full drive mode 50 (20% / 80%) VDDX
Unit
-- pF V
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B.6.1 Master Mode
In Figure B-4 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
3
12
13
BIT 6 . . . 1 9
LSB IN 11 LSB OUT
MSB OUT2
BIT 6 . . . 1
Figure B-4 SPI Master Timing (CPHA=0) In Figure B-5 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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SS1 (OUTPUT) 1 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 2 12 13 3
4
4
12
13
5
6 MSB IN2 BIT 6 . . . 1 11 LSB IN
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9 MOSI (OUTPUT)PORT DATA
1.If configured as output
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure B-5 SPI Master Timing (CPHA=1) In Table B-8 the timing characteristics for master mode are listed. Table B-8 SPI Master Mode Timing Characteristics
Num
1 1 2 3 4 5 6 9 10 11 12 13
C
P P D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi tvsck tvss tho trfi trfo
Min
1/2048 2 -- -- -- 8 8 -- -- 20 -- --
Typ
-- -- 1/2 1/2 1/2 -- -- -- -- -- -- --
Max
1/2 2048 -- -- -- -- -- 30 15 -- 8 8
Unit
fbus tbus tsck tsck tsck ns ns ns ns ns ns ns
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B.6.2 Slave Mode
In Figure B-6 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT)10 7 MISO (OUTPUT) see note 5 MOSI (INPUT) NOTE: Not defined! SLAVE MSB 6 MSB IN BIT 6 . . . 1 LSB IN 2 4 4 12 13 8 9 BIT 6 . . . 1 11 11 SEE NOTE 12 13 3
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SLAVE LSB OUT
Figure B-6 SPI Slave Timing (CPHA=0) In Figure B-7 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
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SS (INPUT) 1 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) see note 7 MOSI (INPUT) NOTE: Not defined! 2 12 13 3
4
4
12
13
9 SLAVE 5 MSB IN MSB OUT 6
11 BIT 6 . . . 1 SLAVE LSB OUT
8
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BIT 6 . . . 1
LSB IN
Figure B-7 SPI Slave Timing (CPHA=1) In Table B-9 the timing characteristics for slave mode are listed. Table B-9 SPI Slave Mode Timing Characteristics
Num
1 1 2 3 4 5 6 7 8 9 10 11 12 13
C
P P D D D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho trfi trfo
Min
DC 4 4 4 4 8 8 -- -- -- -- 20 -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
1/4 -- -- -- -- -- 20 22 30 + tbus
1
Unit
fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns
30 + tbus 1 -- 8 8
NOTES: 1. tbus added due to internal synchronization delay
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B.7 ATD Characteristics
This section describes the characteristics of the analog to digital converter. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.7.1 ATD Operating Characteristics - 5V Range
The Table B-10 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table B-10 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
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Num C
Reference Potential 1 2 3 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 TCONV10 NCONV8 TCONV8 tSR IREF
Min VSSA VDDA/2 4.75 0.5 14 7 3.5 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s s Cycles s s mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK Conv, Time at 4.0MHz3 ATD Clock fATDCLK ATD 8-Bit Conversion Period
5.0
5.25 2.0 28 14 7 26 13 20 0.375
4
D
5 6 7
D
Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
D Stop Recovery Time (VDDA=5.0 Volts) P Reference Supply current
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 3. Reduced accuracy see Table B-13 and Table B-14.
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B.7.2 ATD Operating Characteristics - 3.3V Range
The Table B-11 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.
Table B-11 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Rating
Reference Potential Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 3.0 0.5 14 7 3.5 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s s Cycles s s mA
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1 2 3
D C Differential Reference Voltage D ATD Clock Frequency ATD 10-Bit Conversion Period
3.3
3.6 2.0 28 14 7 26 13 20 0.250
4
D
Clock Cycles1 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK T Conv, Time at 4.0MHz2 ATD Clock fATDCLK ATD 8-Bit Conversion Period
TCONV10 NCONV8 TCONV8 tREC IREF
CONV10
5 6 7
D
Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
D Recovery Time (VDDA=3.3 Volts) P Reference Supply current
NOTES: 1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 2. Reduced accuracy see Table B-13 and Table B-14.
B.7.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. B.7.3.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance are allowed.
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B.7.3.2 Source capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). B.7.3.3 Current injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions.
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2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table B-12 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5
C
C T C C C
Rating
Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 15
Unit
K pF mA A/A A/A
-2.5
2.5 10-4 10-2
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B.7.4 ATD accuracy - 5V Range
Table B-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-13 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num
1 2
C
P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE AE LSB DNL INL AE
Min
-1 -2.0 -2.5
Typ
5
Max
1 2.0 2.5
Unit
mV Counts Counts Counts Counts mV
P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 C 10-Bit Absolute Error at fATDCLK= 4MHz P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
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3 4 5 6 7 8 9
7.0 20 -0.5 -1.0 -1.5 0.5 1.0 0.5 1.0 1.5
Counts Counts Counts
NOTES: 1. These values include quantization error which is inherently 1/2 count for any A/D converter.
B.7.5 ATD accuracy - 3.3V Range
Table B-14 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table B-14 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz Num C
1 2 3 4 5 6 7 8 9 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 C 10-Bit Absolute Error at fATDCLK= 4MHz P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
Rating
Symbol
LSB DNL INL AE AE LSB DNL INL AE
Min
-1.5 -3.5 -5
Typ
3.25
Max
1.5
Unit
mV Counts Counts Counts Counts mV
1.5 2.5 7.0 13
3.5 5
-0.5 -1.5 -2.0 1.0 1.5
0.5 1.5 2.0
Counts Counts Counts
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NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure B-8. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ----------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n Vn - V0
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INL ( n ) =
DNL ( i ) =
------------------- - n 1LSB
i=1
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DNL 10-Bit Absolute Error Boundary
LSB Vi-1
$3FF $3FE $3FD $3FC
Vi
8-Bit Absolute Error Boundary
$FF
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$3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure B-8 ATD Accuracy Definitions NOTE:Figure B-8 shows only definitions, for specification values refer to Table B-13 and Table B-14.
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8-Bit Resolution
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B.8 DAC Characteristics
This section describes the characteristics of the digital to analog converter.
B.8.1 DAC Operating Characteristics
Table B-15 DAC Electrical Characteristics (Operating)
Num
1
C
D D
Characteristic
DAC Supply
Condition
Symbol
VDDA
Min
3.135 -- -- VSSA VDDA/2 -- -200 -40
Typ
-- -- -- -- -- -- -- --
Max
5.5 3.5 1.0 VSSA VDDA 400 1 125
Unit
V mA mA V V mA A
0C
Running DAC Supply Current Stop (low power) Low Reference Potential High Reference Supply Current Input Current, Channel Off1 Operating Temperature Range VREF to VSSA
IDDArun IDDstop VSSA VREF IREF IOFF T
2
D
D
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3 4 5 6
D
D D D
Table B-16 DAC Timing/Performance Characteristics
Num C
D 1 D 2 3 4 5 6 7 D D D D P D Integral Non-Linearity Differential Non-Linearity Resolution Settling Time Absolute Accuracy Offset Error DAC Operating Frequency
Parameters
Condition
VDDA = 3.0V VREF = TBD VDDA = 5.5V VREF = TBD
Symbol
fBUS fBUS INL DNL RES TS ABSACC ERR
Min
--
Typ
--
Max
25
Unit
MHz -- -- -- -- 5 -1 -- 0.25 0.10 -- -- -- +/-2.5 25 -- -- 8 10 1 Count Count Bit s Count mV
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Appendix C External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure C-1 with the actual timing values shown on table Table C-1. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
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Figure C-1 General External Bus Timing
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
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17 Non-Multiplexed Addresses PK5:0 20 ECS PK7 24 R/W PE2
18
19
21
22
23
25
26
27 LSTRB PE3
28
29
30 NOACC PE7 33 IPIPO0 IPIPO1, PE6,5
31
32
34
35
36
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Table C-1 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40C to +140C, CLOAD = 50pF
Num
1 2 3 4 5 6 7
C
P P D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH-tDDW) Address access time(1) (tcyc-tAD-tDSR) E high access time(1) (PWEH-tDSR) Non-multiplexed address delay time Non-muxed address valid to E rise (PWEL-tNAD) Non-multiplexed address hold time Chip select delay time Chip select access time(1) (tcyc-tCSD-tDSR) Chip select hold time Chip select negated time Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tNOD)
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 40 19 19
Typ
Max
25.0
Unit
MHz ns ns ns
8 11 2 7 2 13 0 7 2 12 19 6 6 14 2 16 11 2 8 7 14 2 7 14 2 7 14
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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Table C-1 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40C to +140C, CLOAD = 50pF 32 33 34 35 36 D D D D D NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D) IPIPO[1:0] delay time(1) (PWEH-tP1V) IPIPO[1:0] valid time to E fall tNOH tP0D tP0V tP1D tP1V 2 2 11 2 11 25 7 ns ns ns ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Table C-2 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40C to +140C, CLOAD = 50pF
Num
1 2 3 4 5 6 7
C
P P D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating
Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high1 Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH-tDDW) Address access time(1) (tcyc-tAD-tDSR) E high access time(1) (PWEH-tDSR) Non-multiplexed address delay time Non-muxed address valid to E rise (PWEL-tNAD) Non-multiplexed address hold time Chip select delay time Chip select access time(1) (tcyc-tCSD-tDSR) Chip select hold time Chip select negated time Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tNOD)
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 62.5 30 30
Typ
Max
16.0
Unit
MHz ns ns ns
16 16 2 7 2 15 0 15 2 15 29 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
14 16 2 14 16 2 14 16
ns ns ns ns ns ns ns ns
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Table C-2 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40C to +140C, CLOAD = 50pF 32 33 34 35 36 D D D D D NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D) IPIPO[1:0] delay time(1) (PWEH-tP1V) IPIPO[1:0] valid time to E fall tNOH tP0D tP0V tP1D tP1V 2 2 16 2 11 25 14 ns ns ns ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix D Package Information
D.1 80-pin QFP package
L
60 61 41 40
S
S
B B P
D
S
-BB
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L
0.20 M H A-B
-A-
V 0.05 D
0.20 M C A-B
S
D
-A-,-B-,-DDETAIL A
DETAIL A
21
80 1 20
-DA 0.20 M H A-B 0.05 A-B S 0.20 M C A-B
S S
F
D
S
J D
S
N
E C -CSEATING PLANE
M
DETAIL C -HDATUM PLANE
D 0.20 M C A-B SECTION B-B
S
D
S
H G
0.10 M
VIEW ROTATED 90
U T
DATUM -HPLANE
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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D.2 112-pin LQFP package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M V
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B1
V1
J
AA
28 29 56
57
F D 0.13
M
BASE METAL
N A1 S1 A S
T L-M N
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 11 13 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 R1 0.25
GAGE PLANE
R
C1 (Y) VIEW AB (Z)
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
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Device User Guide End Sheet
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